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參數(shù)資料
| 型號： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 170/211頁 |
| 文件大小： | 1802K |
| 代理商： | S1C88104P0A0100 |
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S1C8F626 TECHNICAL MANUAL
EPSON
53
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
5.7.2 I/O terminal specifications
The serial interface I/O terminals are shared with
the I/O ports, so the terminal specifications are
configured by setting the I/O port registers.
Each I/O port terminal has a built-in pull-up
resistor that is enabled in input mode. Software can
select whether the pull-up resistor is used or not in
port (one bit) units. Use the PULPxx registers to
___________
configure pull-up for the P10 (SIN0), P12 (SCLK0),
___________
P20 (SIN1) and P22 (SCLK1) terminals. When the
pull-up resistor is not used, make sure that the
input terminal does not enter a floating state.
Furthermore, the input interface level (CMOS level
or CMOS Schmitt level) for these terminals can be
selected using the IFLPxx registers of the I/O ports.
Refer to Section 5.6, "I/O Ports", for controlling
pull-up and input interface levels.
The output specification is fixed at complementary
output. Open-drain output cannot be selected and
the high-impedance control function is not pro-
vided.
5.7.3 Transfer modes
There are four transfer modes for the serial inter-
face and mode selection is made by setting the two
bits of the mode selection registers SMDx0 and
SMDx1 as shown in the table below.
Table 5.7.3.1 Transfer modes
SMDx1
SMDx0
Mode
1
0
1
0
1
0
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
Table 5.7.3.2 Terminal settings corresponding
to each transfer mode
Mode
SINx
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
P13/P23
Output
P13/P23
SOUTx SCLKx SRDYx
P12/P22
Input
Output
Input
At initial reset, transfer mode is set to clock syn-
chronous master mode.
■ Clock synchronous master mode
In this mode, the internal clock is utilized as a
synchronous clock for the built-in shift registers,
and clock synchronous 8-bit serial transfers can be
performed with this serial interface as the master.
The synchronous clock is also output from the
_________
SCLKx terminal which enables control of the
external (slave side) serial I/O device. Since the
_________
SRDYx terminal is not utilized in this mode, it can
be used as an I/O port.
Figure 5.7.3.1(a) shows the connection example of
input/output terminals in the clock synchronous
master mode.
■ Clock synchronous slave mode
In this mode, a synchronous clock from the external
(master side) serial input/output device is utilized
and clock synchronous 8-bit serial transfers can be
performed with this serial interface as the slave.
_________
The synchronous clock is input to the SCLKx
terminal and is utilized by this interface as the
synchronous clock.
_________
Furthermore, the SRDYx signal indicating the
transmit-receive ready status is output from the
_________
SRDYx terminal in accordance with the serial
interface operating status.
In the slave mode, the settings for registers SCSx0
and SCSx1 used to select the clock source are
invalid.
Figure 5.7.3.1(b) shows the connection example of
input/output terminals in the clock synchronous
slave mode.
■ Asynchronous 7-bit mode
In this mode, asynchronous 7-bit transfer can be
performed. Parity check during data reception and
addition of parity bit (odd/even/none) during
transmitting can be specified and data processed in
7 bits with or without parity. Since this mode
_________
employs the internal clock, the SCLKx terminal is
_________
not used. Furthermore, since the SRDYx terminal is
not utilized either, both of these terminals can be
used as I/O ports.
Figure 5.7.3.1(c) shows the connection example of
input/output terminals in the asynchronous mode.
■ Asynchronous 8-bit mode
In this mode, asynchronous 8-bit transfer can be
performed. Parity check during data reception and
addition of parity bit (odd/even/none) during
transmitting can be specified and data processed in
8 bits with or without parity. Since this mode
_________
employs the internal clock, the SCLKx terminal is
_________
not used. Furthermore, since the SRDYx terminal is
not utilized either, both of these terminals can be
used as I/O ports.
Figure 5.7.3.1(c) shows the connection example of
input/output terminals in the asynchronous mode.
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