
S1C8F626 TECHNICAL MANUAL
EPSON
61
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
(5) Clock source selection
Select the clock source by writing data to the
two bits of the clock source selection registers
SCSx0 and SCSx1. (See Table 5.7.4.1.)
Since all the registers mentioned in (2)–(5) are
assigned to the same address, it's possible to set
them all with one instruction.
(6) Clock source control
When the programmable timer is selected for
the clock source, set transfer rate on the pro-
grammable timer side. (See "5.10 Programmable
Timer".)
When the divided signal of OSC3 oscillation
circuit is selected for the clock source, be sure
that the OSC3 oscillation circuit is turned ON
prior to commencing data transfer. (See "5.4
Oscillation Circuits and Operating Mode".)
(7) Stop bit length selection
The stop bit length can be configured to 1 bit or
2 bits using the stop bit select register STPBx.
Table 5.7.7.1 Stop bit and parity bit settings
EPRx
1
0
1
0
STPBx
1
0
PMDx
1
0
–
1
0
–
Stop bit
2 bits
1 bit
Parity bit
Odd
Even
Non parity
Odd
Even
Non parity
Settings
(8) Serial data input/output permutation
The S1C8F626 provides the data input/output
permutation select register SDPx to select
whether the serial data bits are transferred from
the LSB or MSB. The SDPx register should be set
before writing data to TRXDx0–TRXDx7.
■ Data transmit procedure
The control procedure and operation during
transmitting is as follows.
(1) Write "0" in the transmit enable register TXENx
to reset the serial interface.
(2) Write "1" in the transmit enable register TXENx
to set into the transmitting enable status.
(3) Write the transmitting data into TRXDx0–
TRXDx7.
Also, when 7-bit data is selected, the TRXDx7
data becomes invalid.
(4) Write "1" in the transmit control bit TXTRGx
and start transmitting.
This control causes the shift clock to change to
enable and a start bit (LOW) is output to the
SOUTx terminal in synchronize to its falling
edge. The transmitting data set to the shift
register is shifted one bit at a time at each falling
edge of the clock thereafter and is output from
the SOUTx terminal. After the data output, it
outputs a stop bit (HIGH) and HIGH level is
maintained until the next start bit is output.
The transmitting complete interrupt factor flag
FSTRAx is set to "1" at the point where the data
transmitting is completed. When interrupt has
been enabled, a transmitting complete interrupt
is generated at this point.
Set the following transmitting data using this
interrupt.
(5) Repeat steps (3) to (4) for the number of bytes of
transmitting data, and then set the transmit
disable status by writing "0" to the transmit
enable register TXENx, when the transmitting is
completed.
Data transmitting
End
TXENx
← 0
No
Yes
Transmit complete ?
Set transmitting data
to TRXDx0–TRXDx7
No
Yes
FSTRAx = 1 ?
TXENx
← 0
TXTRGx
← 1
TXENx
← 1
Fig. 5.7.7.2 Transmit procedure in asynchronous mode