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參數(shù)資料
| 型號： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 169/211頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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52
EPSON
S1C8F626 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
5.7 Serial Interface
5.7.1 Configuration of serial interface
The S1C8F626 incorporates two channels of full
duplex serial interface ports (when asynchronous
system is selected) that allow the user to select
either clock synchronous system or asynchronous
system.
The data transfer method can be selected in soft-
ware.
When the clock synchronous system is selected, 8-
bit data transfer is possible.
When the asynchronous system is selected, either 7-
bit or 8-bit data transfer is possible, and a parity
check of received data and the addition of a parity
bit for transmitting data can automatically be done
by selecting in software.
Figure 5.7.1.1 shows the configuration of the serial
interface.
Note: Channels 0 and 1 of the serial interface are
precisely identical, and the signal and
register names are identified by the channel
number (0 or 1) attached (e.g. the SIN0
terminal is for channel 0 and SIN1 terminal
is for channel 1). This section explains the
serial interface functions in common to both
channels using common signal names with
"x" attached as a substitute for the channel
number (e.g. SIN0/SIN1
→ SINx) except the
part that needs distinction.
Serial interface Ch.0 input/output terminals, SIN0,
_________
SOUT0, SCLK0 and SRDY0 are shared with I/O
ports P10–P13. Serial interface Ch.1 input/output
_________
terminals, SIN1, SOUT1, SCLK1 and SRDY1 are
shared with I/O ports P20–P23. In order to utilize
these terminals for the serial interface input/output
terminals, "1" must be written to the ESIFx register.
Data bus
SOUT0(P11)/
SOUT1(P21)
Serial I/O control
& status register
Received
data buffer
Interrupt
control circuit
Serial input
control circuit
Received data
shift register
Transmitting data
shift register
Serial output
control circuit
SIN0(P10)/
SIN1(P20)
Clock
control circuit
READY output
control circuit
SCLK0(P12)/
SCLK1(P22)
Error detection
circuit
SRDY0(P13)/
SRDY1(P23)
Start bit
detection circuit
Programmable timer 1 underflow signal (Ch.0)
Programmable timer 7 underflow signal (Ch.1)
Interrupt
request
Fig. 5.7.1.1 Configuration of serial interface
At initial reset, these terminals are set as I/O port
terminals.
The direction of I/O port terminals set for serial
interface input/output terminals are determined by
the signal and transfer mode for each terminal.
Furthermore, the settings for the corresponding I/
O control registers for the I/O ports become
invalid.
Table 5.7.1.1 Configuration of input/output terminals
Terminal
When serial interface is selected
P10
P11
P12
P13
P20
P21
P22
P23
SIN0
SOUT0
SCLK0
SRDY0
SIN1
SOUT1
SCLK1
SRDY1
* The terminals used may vary depending on the transfer mode.
The serial interface terminals are configured
according to the transfer mode set using the
registers SMDx0 and SMDx1. SINx and SOUTx are
serial data input and output terminals which
function identically in clock synchronous system
_________
and asynchronous system. SCLKx is exclusively for
use with clock synchronous system and functions
as a synchronous clock input/output terminal.
_________
SRDYx is exclusively for use in clock synchronous
slave mode and functions as a send-receive ready
signal output terminal.
When asynchronous system is selected, since
_________
SCLKx and SRDYx are superfluous, the I/O port
terminals P12/P22 and P13/P23 can be used as I/O
ports.
In the same way, when clock synchronous master
_________
mode is selected, since SRDYx is superfluous, the I/
O port terminal P13/P23 can be used as I/O port.
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