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參數(shù)資料
| 型號： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 199/211頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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80
EPSON
S1C8F626 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer)
TMD0–TMD7: 00FF41H
The clock timer data can be read out.
Each bit of TMD0–TMD7 and frequency corre-
spondence are as follows:
TMD0: 128 Hz
TMD4: 8 Hz
TMD1: 64 Hz
TMD5: 4 Hz
TMD2: 32 Hz
TMD6: 2 Hz
TMD3: 16 Hz
TMD7: 1 Hz
Since the TMD0–TMD7 is exclusively for reading,
the write operation is invalid.
At initial reset, the timer data is set to "00H".
TMRST: 00FF40HD1
Resets the clock timer.
When "1" is written: Clock timer reset
When "0" is written: No operation
Reading:
Always "0"
The clock timer is reset by writing "1" to the
TMRST.
When the clock timer is reset in the RUN status, it
restarts immediately after resetting. In the case of
the STOP status, the reset data "00H" is maintained.
No operation results when "0" is written to the
TMRST.
Since the TMRST is exclusively for writing, it
always becomes "0" during reading.
TMRUN: 00FF40HD0
Controls RUN/STOP of the clock timer.
When "1" is written: RUN
When "0" is written: STOP
Reading:
Valid
The clock timer starts up-counting by writing "1" to
the TMRUN and stops by writing "0".
In the STOP status, the count data is maintained
until it is reset or set in the next RUN status. Also,
when the STOP status changes to the RUN status,
the data that was maintained can be used for
resuming the count.
At initial reset, the TMRUN is set to "0" (STOP).
PTM0, PTM1: 00FF20HD0, D1
Sets the priority level of the clock timer interrupt.
The two bits PTM0 and PTM1 are the interrupt
priority register corresponding to the clock timer
interrupt. Table 5.8.3.2 shows the interrupt priority
level which can be set by this register.
Table 5.8.3.2 Interrupt priority level settings
At initial reset, this register is set to "0" (level 0).
PTM1
PTM0
Interrupt priority level
1
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
ETM1, ETM2, ETM8, ETM32: 00FF22HD0–D3
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
Valid
The ETM1, ETM2, ETM8 and ETM32 are interrupt
enable registers that respectively correspond to the
interrupt factors for 1 Hz, 2 Hz, 8 Hz and 32 Hz.
Interrupts set to "1" are enabled and interrupts set
to "0" are disabled.
At initial reset, this register is set to "0" (interrupt
disabled).
FTM1, FTM2, FTM8, FTM32: 00FF26HD0–D3
Indicates the clock timer interrupt generation status.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
The FTM1, FTM2, FTM8 and FTM32 are interrupt
factor flags that respectively correspond to the
interrupts for 1 Hz, 2 Hz, 8 Hz and 32 Hz and are
set to "1" at the falling edge of each signal.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
At initial reset, this flag is reset to "0".
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