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參數(shù)資料
| 型號： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 192/211頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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S1C8F626 TECHNICAL MANUAL
EPSON
73
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
TXTRG0: 00FF49HD1
TXTRG1: 00FF4DHD1
Functions as the transmitting start trigger and the
operation status indicator (transmitting/stop
status).
When "1" is read:
During transmitting
When "0" is read:
During stop
When "1" is written: Transmitting start
When "0" is written: Invalid
Starts the transmitting when "1" is written to
TXTRGx after writing the transmitting data.
TXTRGx can be read as the status. When set to "1",
it indicates transmitting operation, and "0" indicates
transmitting stop.
At initial reset, TXTRGx is set to "0" (during stop).
RXEN0: 00FF49HD2
RXEN1: 00FF4DHD2
Sets the serial interface to the receiving enable
status.
When "1" is written: Receiving enable
When "0" is written: Receiving disable
Reading:
Valid
When "1" is written to RXENx, the serial interface
shifts to the receiving enable status and shifts to the
receiving disable status when "0" is written.
Set RXENx to "0" when making the initial settings
of the serial interface and similar operations.
At initial reset, RXENx is set to "0" (receiving
disable).
RXTRG0: 00FF49HD3
RXTRG1: 00FF4DHD3
Functions as the receiving start trigger or prepara-
tion for the following data receiving and the
operation status indicator (during receiving/during
stop).
When "1" is read:
During receiving
When "0" is read:
During stop
When "1" is written: Receiving start/following
data receiving preparation
When "0" is written: Invalid
RXTRGx has a slightly different operation in the
clock synchronous system and the asynchronous
system.
The RXTRGx in the clock synchronous system, is
used as the trigger for the receiving start.
Writes "1" into RXTRGx to start receiving at the
point where the receive data has been read and the
following receive preparation has been done. (In
_________
the slave mode, SRDYx becomes "0" at the point
where "1" has been written into the RXTRGx.)
RXTRGx is used in the asynchronous system for
preparation of the following data receiving. Reads
the received data located in the received data buffer
and writes "1" into RXTRGx to inform that the
received data buffer has shifted to empty. When "1"
has not been written to RXTRGx, the overrun error
flag OERx is set to "1" at the point where the
following receiving has been completed. (When the
receiving has been completed between the opera-
tion to read the received data and the operation to
write "1" into RXTRGx, an overrun error occurs.)
In addition, RXTRGx can be read as the status. In
either clock synchronous mode or asynchronous
mode, when RXTRGx is set to "1", it indicates
receiving operation and when set to "0", it indicates
that receiving has stopped.
At initial reset, RXTRGx is set to "0" (during stop).
TRXD00–TRXD07: 00FF4AH
TRXD10–TRXD17: 00FF4EH
During transmitting
Write the transmitting data into the transmit shift
register.
When "1" is written: HIGH level
When "0" is written: LOW level
Write the transmitting data prior to starting
transmitting.
In the case of continuous transmitting, wait for the
transmitting complete interrupt, then write the
data.
The TRXDx7 becomes invalid for the asynchronous
7-bit mode.
Converted serial data for which the bits set at "1" as
HIGH (VDD) level and for which the bits set at "0"
as LOW (VSS) level are output from the SOUTx
terminal.
During receiving
Read the received data.
When "1" is read:
HIGH level
When "0" is read:
LOW level
The data from the received data buffer can be read
out.
Since the sift register is provided separately from
this buffer, reading can be done during the receive
operation in the asynchronous mode. (The buffer
function is not used in the clock synchronous
mode.)
Read the data after waiting for the receiving
complete interrupt.
When performing parity check in the asynchronous
7-bit mode, "0" is loaded into the 8th bit (TRXDx7)
that corresponds to the parity bit.
The serial data input from the SINx terminal is level
converted, making the HIGH (VDD) level bit "1" and
the LOW (VSS) level bit "0" and is then loaded into
this buffer.
At initial reset, the buffer content is undefined.
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