
A
B
C
H
E
D
F
G
I
J
K
L
M
N
O
P
Q
R
S
T
U
V W X
Y
Z
Index-14
PRODUCT SPECIFICATION
initiator
11-2
limitations
11-17
ordering
11-3
overview
11-1
priorities
11-3
registers
base addresses
11-7
built-in self test
11-7
cache line size
11-6
class code
11-6
command
fields
11-5
command ID
11-3
device ID
11-3
DRAM_BASE
11-7
expansion ROM base address
11-9
header type
11-7
interrupt line
11-9
interrupt pin
11-9
latency timer
11-7
max_lat
11-9
min_gnt
11-9
MMIO_BASE
11-7
revision ID
11-6
status
11-5
fields
11-6
vendor ID
11-3
single word load/store
11-2
target of operations
11-3
PCI references,non-cached
5-8
PCI_ADR
PCI interface MMIO register
11-12
picture
11-10
PCI_DATA
PCI interface MMIO register
11-12
picture
11-10
PCSW
definition
3-2
performance events,cache
5-13
Philips Part Number
1-10
pins
AI_OSCLK
description table
8-1
AI_SCK
description table
8-1
AI_SD
description table
8-1
AI_WS
description table
8-1
AO_OSCLK
description table
9-1
AO_SCK
description table
9-1
complete list
1-2
DC/AC Characteristics
1-11
I/O circuit summary
1-1
MM_CAS#
description table
12-5
MM_CLK[1:0]
description table
12-5
MM_CS#[3:0]
description table
12-5
MM_DQ[31:0]
description table
12-5
MM_DQM
description table
12-5
MM_RAS#
description table
12-5
MM_WE#
description table
12-5
package
1-10
SPDO
description table
10-1
timing
1-15
,
1-16
,
1-17
VI_CLK
description table
6-2
VI_DATA[7:0]
description table
6-2
VI_DATA[8]
6-11
VI_DATA[9:8]
description table
6-2
VI_DATA[9]
6-11
VI_DVALID
description table
6-2
VO_CLK
description table
7-3
VO_DATA[7:0]
description table
7-3
VO_IO1
description table
7-3
VO_IO2
description table
7-3
pixel
mirroring
14-6
missing
14-6
shift bypassing for downscaling
14-8
transformation,scaling
14-7
pixel mirroring
7-12
pixels
mirroring
14-12
planar
data format
14-3
PLL filter
of video out
7-24
polyphase filter
14-1