
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-151
Unsigned quad 8-bit multiply most significant
SYNTAX
[ IF rguard ] quadumulmsb rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then {
temp
←
(zero_ext8to32(rsrc1<7:0>)
×
zero_ext8to32(rsrc2<7:0>))
rdest<7:0>
←
temp<15:8>
temp
←
(zero_ext8to32(rsrc1<15:8>)
×
zero_ext8to32(rsrc2<15:8>))
rdest<15:8>
←
temp<15:8>
temp
←
(zero_ext8to32(rsrc1<23:16>)
×
zero_ext8to32(rsrc2<23:16>))
rdest<23:16>
←
temp<15:8>
temp
←
(zero_ext8to32(rsrc1<31:24>)
×
zero_ext8to32(rsrc2<31:24>))
rdest<31:24>
←
temp<15:8>
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dspmul
89
2
No
—
3
2, 3
DESCRIPTION
As shown below, the
quadumulmsb
operation computes four separate products of the four pairs of corresponding
8-bit bytes of rsrc1 and rsrc2 All bytes are considered unsigned. The most-significant 8 bits of each 16-bit product is
written to the corresponding byte in rdest
The
quadumulmsb
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x0210800e, r40 = 0xffffff02
r10 = 0, r60 = 0x80ff1010, r70 = 0x80ff100f
r20 = 1, r60 = 0x80ff1010, r70 = 0x80ff100f
quadumulmsb r30 r40
→
r50
IF r10 quadumulmsb r60 r70
→
r80
no change, since guard is false
IF r20 quadumulmsb r60 r70
→
r90
r90
←
0x40fe0100
r50
←
0x010f7f00
0
1
3
rsrc1
0
1
3
rsrc2
0
3
rdest
×
×
×
×
2
7
2
7
7
1
2
7
1
Four full-precision
16-bit products
0
7
1
0
7
1
0
7
1
0
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
SEE ALSO
quadavg dspuquadaddui
ifir8ii
quadumulmsb