
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-41
Floating-point divide
SYNTAX
[ IF rguard ] fdiv rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then
rdest
←
(float)rsrc1/ (float)rsrc2
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Recovery
Issue slots
ftough
108
2
No
—
17
16
2
DESCRIPTION
The
fdiv
operation computes the quotient rsrc1
÷
rsrc2and stores the result into rdest All values are in IEEE single-
precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is
denormalized, zero is substituted for the argument before computing the quotient, and the IFZ flag in the PCSW is set.
If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
fdiv
causes an
IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw
operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If any other floating-
point compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR of
all simultaneous updates ORed with the existing PCSW value for that exception flag.
The
fdivflags
operation computes the exception flags that would result from an individual
fdiv
.
The
fdiv
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdestis not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values
Operation
Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e–38),
r83 = 0x80800000 (–1.175494351e–38)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00800000 (1.763241526e–38)
r75 = 0x40400000 (3.0),
r76 = 0x0 (0.0)
fdiv r60 r30
→
r90
r90
←
0xc0400000 (–3.0)
fdiv r40 r60
→
r95
r95
←
0xbf800000 (–1.0)
IF r10 fdiv r40 r80
→
r100
no change, since guard is false
IF r20 fdiv r40 r80
→
r110
r110
←
0x7f400000 (2.552117754e38)
fdiv r40 r81
→
r111
r111
←
0x7f800000 (+INF), IFZ, DBZ flags set
fdiv r82 r83
→
r112
r112
←
0xbfc00000 (-1.5)
fdiv r84 r85
→
r113
r113
←
0xffffffff (QNaN), INV flag set
fdiv r70 r70
→
r120
fdiv r80 r80
→
r125
fdiv r75 r76
→
r126
r120
←
0x3f800000 (1.0)
r125
←
0x3f800000 (1.0)
r126
←
0x7f800000 (+INF), DBZ flag set
SEE ALSO
fdivflags readpcsw
writepcsw
fdiv