
TM1300 Data Book
Philips Semiconductors
A-148
PRODUCT SPECIFICATION
Unsigned byte-wise quad average
SYNTAX
[ IF rguard ] quadavg rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then {
temp
←
(zero_ext8to32(rsrc1<7:0>) + zero_ext8to32(rsrc2<7:0>) + 1) / 2
rdest<7:0>
←
temp<7:0>
temp
←
(zero_ext8to32(rsrc1<15:8>) + zero_ext8to32(rsrc2<15:8>) + 1) / 2
rdest<15:8>
←
temp<7:0>
temp
←
(zero_ext8to32(rsrc1<23:16>) + zero_ext8to32(rsrc2<23:16>) + 1) / 2
rdest<23:16>
←
temp<7:0>
temp
←
(zero_ext8to32(rsrc1<31:24>) + zero_ext8to32(rsrc2<31:24>) + 1) / 2
rdest<31:24>
←
temp<7:0>
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dspalu
73
2
No
—
2
1, 3
DESCRIPTION
As shown below, the
quadavg
operation computes four separate averages of the four pairs of corresponding 8-bit
bytes of rsrc1 and rsrc2 All bytes are considered unsigned. The least-significant 8 bits of each average is written to
the corresponding byte in rdest No overflow or underflow detection is performed.
The
quadavg
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x0201000e, r40 = 0xffffff02
r10 = 0, r60 = 0x9c9c6464, r70 = 0x649c649c
r20 = 1, r60 = 0x9c9c6464, r70 = 0x649c649c
quadavg r30 r40
→
r50
IF r10 quadavg r60 r70
→
r80
IF r20 quadavg r60 r70
→
r90
r50
←
0x81808008
no change, since guard is false
r90
←
0x809c6480
0
1
3
rsrc1
0
1
3
rsrc2
0
3
rdest
+
+
+
+
2
7
2
7
1
1
1
1
7
1
2
0
8
0
8
0
8
0
8
Four full-precision
9-bit sums
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
SEE ALSO
iavgonep dspuquadaddui
ifir8ii
quadavg