
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-21
Invalidate data cache block
SYNTAX
[ IF rguard ] dinvalid(d) rsrc1
FUNCTION
if
rguard
then {
addr
←
rsrc1+ d
if
dcache_valid_addr(addr)
then {
dcache_reset_valid_addr(addr)
dcache_reset_dirty_addr(addr)
}
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmemspec
206
1
7 bits
–256..252 by 4
3
5
DESCRIPTION
The
dinvalid
operation resets the valid and dirty bit of a block in the data cache. Regardless of the block’s dirty
bit, the block is not written back to main memory. The target block of
dinvalid
is the block in the data cache that
contains the byte addressed by rsrc1 + d The d value is an opcode modifier, must be in the range –256 to 252
inclusive, and must be a multiple of 4.
Stall cycles are taken as necessary to complete the invalidate operation. If the target block is not in the cache,
dinvalid
has no effect and no stall cycles are taken.
dinvalid
has no effect on blocks that are in the non-cacheable SDRAM aperture.
dinvalid
does clear the valid
bits of locked blocks.
dinvalid
does not change the replacement status of data-cache blocks.
dinvalid
ensures coherency between caches and main memory by discarding all pending prefetch operations
and by causing all non-empty copyback buffers to be emptied to main memory.
The
dinvalid
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls if the
operation is carried out or not. If the LSB of rguardis 1, the operation is carried out; otherwise, it is not carried out.
EXAMPLES
Initial Values
Operation
Result
dinvalid(0) r30
IF r10 dinvalid(4) r40
r10 = 0
no change and no stall cycles, since
guard is false
r20 = 1
IF r20 dinvalid(8) r50
SEE ALSO
dcb
dinvalid