
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-9
Arithmetic shift right
SYNTAX
[ IF rguard ] asr rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then {
n
←
rsrc2<4:0>
rdest<31:31–n>
←
rsrc1<31>
rdest<30–n:0>
←
rsrc1<30:n>
if rsrc2<31:5> != 0 {
rdest <- rsrc1<31>
}
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
shifter
18
2
No
—
1
1, 2
DESCRIPTION
As shown below, the
asr
operation takes two arguments, rsrc1and rsrc2 Rsrc2specifies an unsigned shift amount,
and rsrc1 is arithmetically shifted right by this amount. If the rsrc2<31:5> value is not zero, then take this as a shift by
32 or more bits. The MSB (sign bit) of rsrc1is replicated as needed to fill vacated bits from the left.
The
asr
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis unchanged.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x7008000f, r20 = 1
r30 = 0x7008000f, r42 = 2
r10 = 0, r30 = 0x7008000f, r44 = 4
r20 = 1, r30 = 0x7008000f, r44 = 4
r40 = 0x80030007, r44 = 4
r30 = 0x7008000f, r45 = 0x1f
r30 = 0x8008000f, r45 = 0x1f
r30 = 0x7008000f, r45 = 0x20
r30 = 0x8008000f, r45 = 0x20
r30 = 0x8008000f, r45 = 0x23
asr r30 r20
→
r50
asr r30 r42
→
r60
IF r10 asr r30 r44
→
r70
IF r20 asr r30 r44
→
r80
asr r40 r44
→
r90
asr r30 r45
→
r100
asr r30 r45
→
r100
asr r30 r45
→
r100
asr r30 r45
→
r100
asr r30 r45
→
r100
r50
←
0x38040007
r60
←
0x1c020003
no change, since guard is false
r80
←
0x07008000
r90
←
0xf8003000
r100
←
0x00000000
r100
←
0xffffffff
r100
←
0x00000000
r100
←
0xffffffff
r100
←
0xffffffff
0
31
rsrc1
0
rsrc2
S
S
S
Right shifter
32 bits from rsrc1
0
3
rdest
2
S
S
S
Intermediate result
(example: n= 3)
rsrc2
S
S
S
31
SEE ALSO
asl asli asri lsl lsli lsr
lsri rol roli
asr