
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-7
Arithmetic shift left
SYNTAX
[ IF rguard ] asl rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then {
n
←
rsrc2<4:0>
rdest<31:n>
←
rsrc1<31–n:0>
rdest<n–1:0>
←
0
if rsrc2<31:5> != 0 {
rdest <- 0
}
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
shifter
19
2
No
—
1
1, 2
DESCRIPTION
As shown below, the
asl
operation takes two arguments, rsrc1 and rsrc2 Rsrc2 specify an unsigned shift amount,
and rdest is set to rsrc1 arithmetically shifted left by this amount. If the rsrc2<31:5> value is not zero, then take this as
a shift by 32 or more bits. Zeros are shifted into the LSBs of rdestwhile the MSBs shifted out of rsrc1are lost.
The
asl
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis unchanged.
EXAMPLES
Initial Values
Operation
Result
r60 = 0x20, r30 = 3
r10 = 0, r60 = 0x20, r30 = 3
r20 = 1, r60 = 0x20, r30 = 3
r70 = 0xfffffffc, r40 = 2
r80 = 0xe, r50 = 0xfffffffe
r30 = 0x7008000f, r60 = 0x20
r30 = 0x8008000f, r45 = 0x80000000
asl r30 r45
→
r100
r30 = 0x8008000f, r45 = 0x23
asl r60 r30
→
r90
IF r10 asl r60 r30
→
r100
IF r20 asl r60 r30
→
r110
asl r70 r40
→
r120
asl r80 r50
→
r125
asl r30 r60
→
r111
r90
←
0x100
no change, since guard is false
r110
←
0x100
r120
←
0xfffffff0
r125
←
0x00000000 (shift by more than 32)
r111
←
0x00000000
r100
←
0x00000000
r100
←
0x00000000
asl r30 r45
→
r100
0
3
rsrc1
3
rsrc2
0
0
0
Left shifter
32 bits from rsrc1
0
3
rdest
3
0
0
0
Intermediate result
(example: n= 3)
rsrc2
0
SEE ALSO
asli asr asri lsl lsli lsr
lsri rol roli
asl