
TM1300 Data Book
Philips Semiconductors
A-152
PRODUCT SPECIFICATION
Read data cache status bits
SYNTAX
[ IF rguard ] rdstatus(d) rsrc1
→
rdest
FUNCTION
if
rguard
then {
set_addr
←
rsrc1+ d
/* set_addr<10:6> selects set */
rdest<9:0>
←
dcache_LRU_set(set_addr)
rdest<17:10>
←
dcache_dirty_set(set_addr)
rdest<31:18>
←
0
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmemspec
203
1
7 bits
–256..252 by 4
3
5
DESCRIPTION
The
rdstatus
operation reads the LRU and dirty bits associated with a set in the data cache and writes these bits
into the destination register rdest The target set in the data cache is determined by bits 10..6 of the result of rsrc1+ d
The dvalue is an opcode modifier, must be in the range –256 to 252 inclusive, and must be a multiple of 4.
The result of
rdstatus
contains LRU information in bits 9..0 and dirty-bit information in bits 17..10. All other bits of
rdestare set to zero.
rdstatus
requires two stall cycles to complete.
The dual-ported data cache uses two separate copies of tag and status information. A
rdstatus
operation returns
the LRU and dirty information stored in the cache port that corresponds to the operation slot in which the
rdstatus
operation is issued.
The
rdstatus
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis not changed.
EXAMPLES
Initial Values
Operation
Result
rdstatus(0) r30
→
r60
IF r10 rdstatus(4) r40
→
r70
IF r20 rdstatus(8) r50
r10 = 0
r20 = 1
no change, since guard is false
→
r80
SEE ALSO
rdtag
rdstatus