
TM1300 Data Book
Philips Semiconductors
A-190
PRODUCT SPECIFICATION
Unsigned 16-bit load with scaled index
SYNTAX
[ IF rguard ] uld16x rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then {
if
PCSW.bytesex = LITTLE_ENDIAN
then
bs
←
1
else
bs
←
0
temp<7:0>
←
mem[rsrc1+ (2
×
rsrc2) + (1
⊕
bs)]
temp<15:8>
←
mem[rsrc1+ (2
×
rsrc2) + (0
⊕
bs)]
rdest
←
zero_ext16to32(temp<15:0>)
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmem
199
2
No
—
3
4, 5
DESCRIPTION
The
uld16x
operation loads the 16-bit memory value from the address computed by rsrc1 + 2
×
rsrc2 zero extends
it to 32 bits, and writes the result in rdest If the memory address computed by rsrc1 + 2
×
rsrc2 is not a multiple of 2,
the result of
uld16x
is undefined but no exception will be raised. This load operation is performed as little-endian or
big-endian depending on the current setting of the bytesex bit in the PCSW.
The result of an access by
uld16x
to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32-bit loads and stores.
The
uld16x
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguardis 1, rdestis written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
uld16x
has no side effects whatever.
EXAMPLES
Initial Values
Operation
Result
r10 = 0xd00, r30 = 1, [0xd02] = 0x22,
[0xd03] = 0x11
r50 = 0, r40 = 0xd04, r20 = 0xfffffffe,
[0xd00] = 0x84, [0xd01] = 0x33
r60 = 1, r40 = 0xd04, r20 = 0xfffffffe,
[0xd00] = 0x84, [0xd01] = 0x33
r70 = 0xd01, r30 = 1
uld16x r10 r30
→
r100
r100
←
0x00002211
IF r50 uld16x r40 r20
→
r80
no change, since guard is false
IF r60 uld16x r40 r20
→
r90
r90
←
0x00008433
uld16x r70 r30
→
r110
r110 undefined (0xd01 + 2
×
1 is not a multi-
ple of 2)
SEE ALSO
uld16 ild16 uld16d ild16d
uld16r ild16r ild16x
uld16x