
Philips Semiconductors
SPDIF Out
PRODUCT SPECIFICATION
10-5
10.14 MMIO REGISTER DESCRIPTION
Figure 10-4. SPDO unit status/control field MMIO layout.
MMIO_base
offset:
SPDO_STATUS (r/
0x10 4C00
SPDO_CTL (r/w)
0x10 4C04
SPDO_FREQ (r/w)
0x10 4C08
SPDO_BASE1 (r/w)
0x10 4C0C
FREQUENCY
BUF1_ACTIVE
UNDERRUN
HBE (Highway bandwidth error)
SPDO_BASE2 (r/w)
0x10 4C10
BASE2
SPDO_SIZE (r/w)
0x10 4C14
SIZE (in bytes)
31
0
3
7
11
15
19
23
27
BASE1
BUF2_EMPTY
BUF1_EMPTY
RESET
TRANS_ENABLE
TRANS_MODE
LITTLE_ENDIAN
SLEEPLESS
0
UDR_INTEN
HBE_INTEN
BUF2_INTEN
BUF1_INTEN
ACK_UDR
ACK_HBE
ACK_BUF2
ACK_BUF1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
3
7
11
15
19
23
27
31
0
3
7
11
15
19
23
27
SPDO_TSTAMP (r/o)
0x10 4C18
TIMESTAMP
Table 10-4. SPDO_STATUS MMIO register
field
type
description
BUF1_EMPTY
r/o
Sticky flag - set if DMA buffer 1 emp-
tied by the SPDO hardware. Can only
be cleared by software write to
ACK_BUF1.
Sticky flag - set if DMA buffer 2 emp-
tied by the SPDO hardware. Can only
be cleared by software write to
ACK_BUF2.
Highway Bandwidth Error. Sticky flag -
set if internal SPDO buffers emptied
beforenew data brought from memory.
Refer to
Section 10.17, “HBE and
Highway Latency.”
Can be cleared
only by a software write to ACK_HBE.
Sticky flag - set if both DMA buffers
were emptied before a new full buffer
was assigned by the DSPCPU. The
hardware has performed a normal
buffer switch over and is emitting old
data. Can only be cleared by software
write to ACK_UDR.
Flag - set if the hardware is currently
emitting DMA buffer 1 data; negated
when emitting DMA buffer 2 data.
BUF2_EMPTY
r/o
HBE
r/o
UNDERRUN
r/o
BUF1_ACTIVE
r/o
Table 10-5. SPDO_CTL MMIO register
field
type
description
ACK_BUF1
w/o
Always reads as ‘0’. Write a ‘1’ here
to clear BUF1_EMPTY. This
informs SPDO that DMA buffer 1 is
now full. Writing a ‘0’ has no effect.
Always reads as ‘0’. Write a ‘1’ here
to clear BUF2_EMPTY. This
informs SPDO that DMA buffer 2 is
now full. Writing a ‘0’ has no effect.
Always reads as ‘0’. Writing a ‘1’
here clears HBE.
Always reads as ‘0’. Writing a ‘1’
here clears UNDERRUN.
If BUF1_EMPTY asserted and this
bit asserted, the SRC 25 interrupt
line is asserted.
If BUF2_EMPTY asserted and this
bit asserted, the SRC 25 interrupt
line is asserted.
If HBE asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.
If UNDERRUN asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.
ACK_BUF2
w/o
ACH_HBE
w/o
ACK_UDR
w/o
BUF1_INTEN
r/w
BUF2_INTEN
r/w
HBE_INTEN
r/w
UDR_INTEN
r/w