
TM1300 Data Book
Philips Semiconductors
A-20
PRODUCT SPECIFICATION
Data cache copy back
SYNTAX
[ IF rguard ] dcb(d) rsrc1
FUNCTION
if
rguard
then {
addr
←
rsrc1+ d
if
dcache_valid_addr(addr) && dcache_dirty_addr(addr)
then {
dcache_copyback_addr(addr)
dcache_reset_dirty_addr(addr)
}
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmemspec
205
1
7 bits
–256..252 by 4
3
5
DESCRIPTION
The
dcb
operation causes a block in the data cache to be copied back to main memory if the block is marked dirty
and valid, and the block’s dirty bit is reset. The target block of
dcb
is the block in the data cache that contains the byte
addressed by rsrc1 + d The d value is an opcode modifier, must be in the range –256 to 252 inclusive, and must be a
multiple of 4.
A valid copy of the target block remains in the cache. Stall cycles are taken as necessary to complete the copy-back
operation. If the target block is not dirty or if the block is not in the cache,
dcb
has no effect and no stall cycles are
taken.
dcb
has no effect on blocks that are in the non-cacheable SDRAM aperture.
dcb
does not change the replacement
status of data-cache blocks.
dcb
ensures coherency between caches and main memory by discarding all pending prefetch operations and by
causing all non-empty copyback buffers to be emptied to main memory.
The
dcb
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls if the
operation is carried out or not.If the LSB of rguard is 1, the operation is carried out; otherwise,it is not carried out.
EXAMPLES
Initial Values
Operation
Result
dcb(0) r30
IF r10 dcb(4) r40
r10 = 0
no change and no stall cycles, since
guard is false
r20 = 1
IF r20 dcb(8) r50
SEE ALSO
dinvalid
dcb