
TM1300 Data Book
Philips Semiconductors
A-54
PRODUCT SPECIFICATION
IEEE status flags from floating-point multiply
SYNTAX
[ IF rguard ] fmulflags rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then
rdest
←
ieee_flags((float)rsrc1
×
(float)rsrc2)
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ifmul
143
2
No
—
3
2, 3
DESCRIPTION
The
fmulflags
operation computes the IEEE exceptions that would result from computing the product rsrc1
×
rsrc2
and stores a bit vector representing the exception flags into rdest The argument values are in IEEE single-precision
floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as the IEEE
exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is according
to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before computing the
product, and the IFZ bit in the result is set. If the product would be denormalized, the OFZ bit in the result is set.
The
fmulflags
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis not changed.
EXAMPLES
Initial Values
Operation
Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r41 = 0x3f000000 (0.5),
r80 = 0x00800000 (1.17549435e–38)
r42 = 0x7f800000 (+INF),
r43 = 0x0 (0.0)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e–38),
r83 = 0x8080000 (–1.175494351e–38)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00800000 (1.763241526e–38)
fmulflags r60 r30
→
r90
r90
←
0
fmulflags r40 r60
→
r95
r95
←
0
IF r10 fmulflags r40 r80
→
r100
no change, since guard is false
IF r20 fmulflags r40 r80
→
r105
r105
←
0
fmulflags r41 r80
→
r110
r110
←
0x46 (OFZ UNF INX)
fmulflags r42 r43
→
r106
r106
←
0x10 (INV)
fmulflags r40 r81
→
r111
r111
←
0x20 (IFZ)
fmulflags r82 r83
→
r112
r112
←
0x06 (UNF INX)
fmulflags r84 r85
→
r113
r113
←
0
fmulflags r70 r70
→
r120
fmulflags r80 r80
→
r125
r120
←
0x0a (OVF INX)
r125
←
0x06 (UNF INX)
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
0
31
0
SEE ALSO
fmul faddflags readpcsw
fmulflags