
Philips Semiconductors
PCI-XIO External I/O Bus
PRODUCT SPECIFICATION
22-5
22.3
DATA FORMATS
The data transfer formats for the PCI-XIO bus are shown
in
Figure 22-5
. The 8-bit data field is the data transferred
to or from the PCI-XIO Bus. The read address is the 24-
bit address on the PCI-XIO Bus address lines when the
read transfer takes place.
22.4
INTERFACE
22.4.1
PCI-XIO Bus Interface Design
The PCI-XIO Bus can accommodate a variety of different
devices and bus protocols. The following are examples
of devices interfaced to the PCI-XIO Bus.
Data
Read Address
Unused
Data
Read: XIO Bus to PCI
Write: PCI to XIO Bus
31 24 23 0
31 24 23 0
Figure 22-5. PCI-XIO Bus data formats
Table 22-1. PCI-XIO Bus signal definitions
TM1300 PCI Signal
Pins
I/O
PCI Function
XIO Function
PCI_INTB#
PCI_AD[23:0]
PCI_AD[31:24]
PCI_PAR
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
PCI_CLK
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_IDSEL#
PCI_REQ#
PCI_GNT#
PCI_PERR#
PCI_SERR
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
1
24
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
O
I/O
I/O
O
PCI-XIO Bus Enable = XIO Bus Active As Target Device
PCI Address/Data
Address bus: 16 MB
Data bus: 8 bits
Even Parity for AD & C/BE
Command/Byte Enables
On XIO read, BE[3:0] = 0110b’4
On XIO write, BE[3:0] = 0111b’4
IORD# = Read Enable
IOWR# = Write Enable
DS# = Data Strobe
unused
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
O
I/O
I/O
I/O
I/O
33 MHz PCI Clock: can optionally be generated by TM1300 on board osc
PCI Address/Command Strobe + Transfer In Progress
Device Select Valid
Initiator Ready = Transfer In Progress
Target Ready
Target Requests Stop of Transaction
Chip Select for PCI Config Writes
TM1300 Requesting PCI Bus
TM1300 Is Granted PCI Bus
Parity Error to TM1300
System Error from TM1300
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
Asserted by TM1300 = XIO Active
Asserted by TM1300 = XIO Transfer Timing
XIO Bus Active = Global Chip Select