
TM1300 Data Book
Philips Semiconductors
1-4
PRODUCT SPECIFICATION
PCI_AD00
PCI_AD01
PCI_AD02
PCI_AD03
PCI_AD04
PCI_AD05
PCI_AD06
PCI_AD07
PCI_AD08
PCI_AD09
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
PCI_PAR
PCI_FRAME#
T1
R3
R2
R1
P2
P1
N2
N1
M2
M1
L2
L1
K1
K2
J1
J2
D1
D3
C1
B2
B1
C3
A1
A3
C4
B4
A4
A5
C6
B6
A6
M3
J3
D2
B3
H1
E2
PCI
I/O
Multiplexed address and data.
PCI
I/O
Multiplexed bus commands and byte enables. High for command, low for byte enable.
PCI
PCI
I/O
I/O
Even parity across AD and C/BE lines.
Sustained tri-state. Frame is driven by a master to indicate the beginning and duration
of an access.
Sustained tri-state. Initiator Ready indicates that the bus master is ready to complete
the current data phase.
Sustained tri-state. Target Ready indicates that the bus target is ready to complete the
current data phase.
Sustained tri-state. Indicates that the target is requesting that the master stop the cur-
rent transaction.
Used as chip select during configuration read/write cycles.
Sustained tri-state. Indicates whether any device on the bus has been selected.
Driven by TM1300 as PCI bus master to request use of the PCI bus.
Indicates to TM1300 that access to the bus has been granted.
Sustained tri-state. Parity error generated/received by TM1300.
System error. This signal is asserted when operating as target and detecting an
address parity error.
PCI_IRDY#
E1
PCI
I/O
PCI_TRDY#
F3
PCI
I/O
PCI_STOP#
G2
PCI
I/O
PCI_IDSEL
PCI_DEVSEL#
PCI_REQ#
PCI_GNT#
PCI_PERR#
PCI_SERR#
A2
F1
B7
B5
G1
H2
PCI
PCI
PCI
PCI
PCI
PCI
IN
I/O
I/O
IN
I/O
OD
Pin Name
BGA
Ball
Pad
Type
Mode
Description