
TM1300 Data Book
Philips Semiconductors
A-40
PRODUCT SPECIFICATION
IEEE status flags from floating-point add
SYNTAX
[ IF rguard ] faddflags rsrc1 rsrc2
→
rdest
FUNCTION
if
rguard
then
rdest
←
ieee_flags((float)rsrc1+ (float)rsrc2)
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
falu
112
2
No
—
3
1, 4
DESCRIPTION
The
faddflags
operation computes the IEEE exceptions that would result from computing the sum rsrc1+rsrc2
and stores a bit vector representing the exception flags into rdest The argument values are in IEEE single-precision
floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as the IEEE
exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is according
to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before computing the
sum, and the IFZ bit in the result is set. If the sum would be denormalized, the OFZ bit in the result is set.
The
faddflags
operation optionally takes a guard, specified in rguard If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguardis 1, rdestis written; otherwise, rdestis not changed.
EXAMPLES
Initial Values
Operation
Result
r10 = 0x7f7fffff (3.402823466e+38),
r20 = 0x3f800000 (1.0)
r30 = 0,
r10 = 0x7f7fffff (3.402823466e+38)
r40 = 1,
r10 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00a00000 (1.469367939e–38),
r81 = 0x80800000 (–1.17549435e–38)
r95 = 0x7f800000 (+INF),
r96 = 0xff800000 (–INF)
r98 = 0x40400000 (3.0),
r99 = 0x00400000 (5.877471754e–39)
faddflags r10 r20
→
r60
r60
←
0x2 (INX)
IF r30 faddflags r10 r10
→
r50
no change, since guard is false
IF r40 faddflags r10 r10
→
r70
r70
←
0xa (OVF INX)
faddflags r80 r81
→
r100
r100
←
0x46 (OFZ UNF INX)
faddflags r95 r96
→
r105
r105
←
0x10 (INV)
faddflags r98 r99
→
r111
r111
←
0x20 (IFZ)
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
0
31
0
SEE ALSO
fadd fsubflags readpcsw
faddflags