參數(shù)資料
型號(hào)： PCF5083
廠商： NXP Semiconductors N.V.
英文描述： STEEL COVER
中文描述： GSM信號(hào)處理IC
文件頁(yè)數(shù)： 40/136頁(yè)
文件大?。?/td> 602K
代理商： PCF5083
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1996 Oct 29
40
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
8.5.4
M
ONITOR
C
HANNEL
R
ECEIVER
P
ROTOCOL
After IOMCON_REG[MASTERx_EN] is set to a logic 1,
the receiver state machine is in an idle state and waits
for the first byte transmission. The input buffer full flag
MONx_IBF is cleared. The MR flag is sent as a logic 1
in accordance with the IOM
-2 specification.
After the reception of a data byte the MONx_IBF flag is
set and the System Controller may read the data from
MONx_REG.
A full handshake is implemented in accordance with
IOM
-2 specification. The receiver may delay the data
transmission if the input buffer is full and the System
Controller does not read the buffer in time. In this case
MR = 0 is maintained until MONx_REG is read. The
MONx_IBF flag is cleared with the data read access.
The transmitter may delay the data transmission if it
delays the next byte valid indication. In this case MR = 0
is maintained in subsequent frames.
If an end of transmission is detected the receiver state
machine gets into the idle state. The REOMx flag in
IOMCTRL_REG is set. REOMx = 1 also asserts the
IOM
-2 interrupt (IOMx_IBF_EN is used as enable bit)
to indicate the end of transmission to the System
Controller. The REOMx flag is cleared with a dummy
read of MONx_REG.
To send an abort request the TABORTx flag in
IOMCTRL_REG is set. The receiver state machine
enters the idle state. The TABORTx flag is reset after the
procedure.
Time-outs are not detected. Collision detection and the
maximum speed case is not supported.
8.5.5
C
OMMAND
/I
NDICATION
C
HANNEL
T
RANSMITTER
All data words are sent at least in two subsequent frames.
If the transmitter runs out of data the last data word is
repeated. The flags CI0(1)_IBF and CI0(1)_OBE are
provided to indicate the input/output register status.
8.5.6
C
OMMAND
/I
NDICATION
C
HANNEL
R
ECEIVER
If the received data is different from the data input buffer
the new data pattern is loaded into the data input buffer.
The CI0(1)_IBF flag is cleared if it is set. If during the next
frame the received data is identical to the data stored in the
data input buffer the buffer contents is considered valid
and the CI0(1)_IBF flag is set. The System Controller now
has to fetch the data within the next 125
μ
s, otherwise data
might be lost.
8.5.7
A
UDIO
I
NTERFACE
The Audio Interface provides the translation of one 16-bit
IOM
-2 timeslot into a timing according to Chapter 16 for
the receive and transmit direction. The operation of the
interface is configurable with the flags of register
ACON_REG. The Audio Interface is enabled or disabled
under control of the DSP core with IO1/AEN = 1.
Otherwise the data word 00H is sent in both directions.
With ACON_REG[TRANS_EN] = 1, a transparent mode is
selected. In this mode the internal IOM
-2 signals FSC
and DCL are directly connected to ACLK and AFS. ADI is
directly connected to A_OUT or B_OUT and ADO to A_IN
or B_IN.
The following should be noted:
The flags in register ACON_REG should only be
changed when the Audio Interface is disabled with
IO1/AEN = 0
The Audio Interface can only operate in the transparent
mode if a timing mode is selected which results in only
one 16-bit timeslot on the IOM
-2 side
The frequency of ACLK must be chosen such that the
complete transmission of a 16-bit word via the Audio
Interface does not exceed the duration of N-1 timeslots,
with N equal to the number of 16-bit timeslots on the
IOM
-2 side
Jitter is not allowed on AFS and ACLK as audio data
might get corrupted.
Table 25
Audio Interface configuration register (ACON_REG)
BIT
FLAG
OPERATION (if bit is set)
0
1
2
3
TX_EN
TX_DEST
RX_EN
RX_SOURCE
TX_SLOT0 to TX_SLOT3
RX_SLOT0 to RX_SLOT3
TRANS_EN
Enable transmit direction (ADI to IOM
-2).
Select output to IOM
-2. A logic 0 selects A_OUT; a logic 1 selects B_OUT.
Enable receive direction (IOM
-2 to ADO).
Select input from IOM
-2. A logic 0 selects A_IN; a logic 1 selects B_IN.
IOM
-2 timeslot translated from the transmit section (0 to 15).
IOM
-2 timeslot translated from the receive section (0 to 15).
Enable transparent mode.
4 to 7
8 to 11
12
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參數(shù)描述
PCF5083H/001/F2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF5083H/5V2/F3 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
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PCF51AC128ACFUE 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
PCF51AC128ACLKE 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
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