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參數(shù)資料
| 型號(hào)： | PCF5083 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | STEEL COVER |
| 中文描述： | GSM信號(hào)處理IC |
| 文件頁(yè)數(shù)： | 11/136頁(yè) |
| 文件大小： | 602K |
| 代理商： | PCF5083 |
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1996 Oct 29
11
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
7
OVERVIEW OF THE GSM CHIP SET
7.1
General
The chip set’s high-level architectural modularity ensures
that it can be easily adapted to meet various market
requirements in terms of hardware and software. Figure 4
is a simplified block diagram of a GSM terminal using the
Philips Semiconductors chip set.
The receiver converts the antenna input signal from
890 to 915 MHz down into a complex baseband signal
consisting of an in-phase (I) and a quadrature
component (Q). In order to deal with the high dynamic
range from
104 to
10 dBm, the receiver provides an
AGC input controlled by the layer 1 software in the System
Controller. The complex baseband signal is connected to
the input of the PCF5072 baseband interface IC. This IC
samples the I and Q components at the GSM bit clock
(270 kHz) with an accuracy of approximately 2
×
13 bits.
The equalizer is responsible for the following tasks:
Channel impulse response estimation and bit
synchronization by means of the training sequence
Adaptive channel equalization with a modified Maximum
Likelihood Sequence Estimation (MLSE) approach that
produces a bit-by-bit soft decision information (Channel
Measurement Information (CMI)
Channel impulse response adaption and frequency
offset estimation.
After decryption the channel decoder performs
convolutional and block decoding. Depending on the
logical channel in use, there are decoding schemes for
TCH/F (FACCH/F), SACCH and SDCCH.
The speech decoder synthesises the audio signal from the
received bit stream. Updating of comfort noise parameters
occurs each time a valid Silence Descriptor (SID) is
received. Comfort noise is inserted during periods of
speech pauses. Substitution and muting of lost or bad
frames is implemented.
The full rate speech encoder collects speech samples of
13-bit uniform PCM format (104 kbits/s) and compresses
them to 13 kbits/s according to the linear predictive coding,
long term prediction, Regular Pulse Excitation (RPE-LTP).
Discontinuous Transmission (DTX) is available (voice
activity detection, background acoustic noise).
To protect the data from transmission errors, block and
convolutional coders form the channel encoder. The
encoding modules relates to the logical channels (e.g.
RACH, TCH/F (FACCH/F), SDCCH/SACCH).
After encryption the burst builder generates either Normal
Bursts (NB) or Access Bursts (AB). The bit-stream is then
modulated with a GMSK modulator (Gaussian Minimum
Shift Keying) and upconverted in a quadrature mixer to
890 to 915 MHz.
The on-chip GSM timer generates all power-down and
control signals for the receiver, the transmitter, the
P90CL301 System Controller and the PCF5072 baseband
interface IC.
The System Controller (P90CL301) services all HW
interfaces and performs the signalling software contained
in the GSM layer stack (with L1, L2, L3, O&M, UAP,
SIMAP etc).
The voiceband ADCs and DACs of the PCF5072 perform
the conversion between the analog audio signals and the
digital domain.
7.2
The role of the PCF5083
The PCF5083 is a dedicated VLSI circuit offering
baseband signal processing tasks for the Pan European
Global System for Mobile telecommunication (GSM). The
PCF5083 can be applied in GSM mobile stations or
hand-helds. The embedded DSP core is optimized for
GSM baseband functions and contains an on-chip
program ROM featuring the following tasks:
Full rate speech coding/decoding including VAD/DTX
(“GSM 06 series”)
Encryption/decryption according to both A5/1 and A5/2
algorithms (“GSM Rec. 3.20, 3.21”)
Burst building supporting access burst and normal burst
(“GSM Rec. 5.02”)
Frequency Correction Burst (FCB) detection and
evaluation
Synchronization burst (SCH) detection
BCCH monitoring of neighbouring cells
Channel coding/decoding and
interleaving/de-interleaving (“GSM Rec. 5.03”) for:
– Broadcast Channels (BCH): SCH, BCCH
– Common Control Channels (CCCH): PCH, RACH,
AGCH
– Dedicated Control Channels (DCH): SDCCH,
SACCH
– Traffic Channels (TCH): TCH/FS, TCH/F2.4,
TCH/F4.8, TCH/F9.6, TCH/H4.8 and TCH/H2.4
– Associated Control Channels (ACCH): FACCH and
SACCH
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PCF5083H/001/F2 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/5V2/F3 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/F2 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF51AC128ACFUE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| PCF51AC128ACLKE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
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