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參數(shù)資料
| 型號： | PCF5083 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | STEEL COVER |
| 中文描述： | GSM信號處理IC |
| 文件頁數(shù)： | 14/136頁 |
| 文件大?。?/td> | 602K |
| 代理商： | PCF5083 |
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1996 Oct 29
14
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
8
FUNCTIONAL DESCRIPTION TIMER CORE
8.1
Clock generator
The Clock Generator consists of a low swing input buffer
for the 13 MHz reference clock, a PLL as frequency
multiplier and a 32.768 kHz crystal oscillator. The PLL
generates 13 MHz, 39 MHz and 52 MHz from the 13 MHz
reference clock. The PLL reset inputRSTP is used to bring
the PLL into a low-power state when set to a LOW level.
The 13 MHz reference clock is AC coupled to input CKI.
CKI is a reduced swing input which requires a signal in the
range of 0.7 V
(p-p)
(worst case) for operation. The clock
signal is amplified and used as the input clock for the PLL.
The Timer core is either clocked with the 13 MHz
reference clock or the 13 MHz PLL output. The clock
source is selected with input CLKSEL as shown in Table 1.
Table 1
Timer Core clock selection
CLKSEL
TIMER CORE CLOCK
0
1
PLL output
buffered CKI input
Using the PLL output reduces the tolerance requirements
for the duty cycle of the reference clock.
The DSP core will function with the 39 MHz PLL clock or
the clock supplied from DCLK. The clock source is
selected with the flags in SYSCON_REG; see Tables 2
and 3. Within the DSP core the selected clock is first
halved before use. The 52 MHz PLL is register selectable
for future applications but should not be used in the current
implementation of this device
The inverting buffer stage between CLK32I and CLK32O,
together with an external crystal network generates a
32.768 kHz clock for the Timer Core. This clock is used for
the real time clock, the ON/OFF logic etc.
The internal 13 MHz, 19.5 MHz and 2b/2c: 32.768 kHz/
3: 26 MHz clocks are externally available for other system
components, e.g. the microcontroller. All clock outputs can
be disabled if they are not used to reduce the power
consumption.
Table 2
System Configuration Register (SYSCON); note 1
Note
1.
2.
3.
Default value after reset 0X00 0000b (x: LOCK is undefined).
Versions PCF5083-2b and PCF5083-2c only.
PCF5083-3 only.
BIT
FLAG
R/W
R
DESCRIPTION
7
6
LOCK
Reserved
PLL lock select.
If LOCK = 0; then PLL in lock. If LOCK = 1; then PLL out of
lock.
RS232 interface clock source.
If RS232_CLK = 0; then the 13 MHz Timer
clock is used. If RS232_CLK = 1; then the RS232 clock is supplied via the ADI
pin (pin 125).
DSP clock select.
This two bits select the DSP clock frequency; see Table 3.
5
RS232_CLK
W
4
3
2
DSP_CLK1
DSP_CLK0
CLK32K
(2)
W
W
W
CLK32K output enable/disable.
If CLK32K = 0; then the CLK32K output is
enabled. If CLK32K = 1; then the CLK32K output is disabled.
CLK26M output enable/disable.
If CLK26M = 0; then the CLK26M output is
enabled. If CLK26M = 1; then the CLK26M output is disabled.
CLK20M output enable/disable.
If CLK20M = 0; then the CLK20M output is
enabled. If CLK20M = 1; then the CLK20M output is disabled.
CLK13M output enable/disable.
If CLK13M = 0; then the CLK13M output is
enabled. If CLK13M = 1; then the CLK13M output is disabled.
CLK26M
(3)
1
CLK20M
W
0
CLK13M
W
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相關(guān)代理商/技術(shù)參數(shù) |
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| PCF5083H/001/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/5V2/F3 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF51AC128ACFUE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
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