參數(shù)資料
型號(hào)： PCF5083
廠商： NXP Semiconductors N.V.
英文描述： STEEL COVER
中文描述： GSM信號(hào)處理IC
文件頁(yè)數(shù)： 14/136頁(yè)
文件大?。?/td> 602K
代理商： PCF5083
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)
1996 Oct 29
14
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
8
FUNCTIONAL DESCRIPTION TIMER CORE
8.1
Clock generator
The Clock Generator consists of a low swing input buffer
for the 13 MHz reference clock, a PLL as frequency
multiplier and a 32.768 kHz crystal oscillator. The PLL
generates 13 MHz, 39 MHz and 52 MHz from the 13 MHz
reference clock. The PLL reset inputRSTP is used to bring
the PLL into a low-power state when set to a LOW level.
The 13 MHz reference clock is AC coupled to input CKI.
CKI is a reduced swing input which requires a signal in the
range of 0.7 V
(p-p)
(worst case) for operation. The clock
signal is amplified and used as the input clock for the PLL.
The Timer core is either clocked with the 13 MHz
reference clock or the 13 MHz PLL output. The clock
source is selected with input CLKSEL as shown in Table 1.
Table 1
Timer Core clock selection
CLKSEL
TIMER CORE CLOCK
0
1
PLL output
buffered CKI input
Using the PLL output reduces the tolerance requirements
for the duty cycle of the reference clock.
The DSP core will function with the 39 MHz PLL clock or
the clock supplied from DCLK. The clock source is
selected with the flags in SYSCON_REG; see Tables 2
and 3. Within the DSP core the selected clock is first
halved before use. The 52 MHz PLL is register selectable
for future applications but should not be used in the current
implementation of this device
The inverting buffer stage between CLK32I and CLK32O,
together with an external crystal network generates a
32.768 kHz clock for the Timer Core. This clock is used for
the real time clock, the ON/OFF logic etc.
The internal 13 MHz, 19.5 MHz and 2b/2c: 32.768 kHz/
3: 26 MHz clocks are externally available for other system
components, e.g. the microcontroller. All clock outputs can
be disabled if they are not used to reduce the power
consumption.
Table 2
System Configuration Register (SYSCON); note 1
Note
1.
2.
3.
Default value after reset 0X00 0000b (x: LOCK is undefined).
Versions PCF5083-2b and PCF5083-2c only.
PCF5083-3 only.
BIT
FLAG
R/W
R
DESCRIPTION
7
6
LOCK
Reserved
PLL lock select.
If LOCK = 0; then PLL in lock. If LOCK = 1; then PLL out of
lock.
RS232 interface clock source.
If RS232_CLK = 0; then the 13 MHz Timer
clock is used. If RS232_CLK = 1; then the RS232 clock is supplied via the ADI
pin (pin 125).
DSP clock select.
This two bits select the DSP clock frequency; see Table 3.
5
RS232_CLK
W
4
3
2
DSP_CLK1
DSP_CLK0
CLK32K
(2)
W
W
W
CLK32K output enable/disable.
If CLK32K = 0; then the CLK32K output is
enabled. If CLK32K = 1; then the CLK32K output is disabled.
CLK26M output enable/disable.
If CLK26M = 0; then the CLK26M output is
enabled. If CLK26M = 1; then the CLK26M output is disabled.
CLK20M output enable/disable.
If CLK20M = 0; then the CLK20M output is
enabled. If CLK20M = 1; then the CLK20M output is disabled.
CLK13M output enable/disable.
If CLK13M = 0; then the CLK13M output is
enabled. If CLK13M = 1; then the CLK13M output is disabled.
CLK26M
(3)
1
CLK20M
W
0
CLK13M
W
相關(guān)PDF資料
PDF描述
PCF84C12A 8-BIT MICROCONTROLLER
PCF84C12AP 8-BIT MICROCONTROLLER
PCF84C12AT 8-BIT MICROCONTROLLER
PCF84C21A Telecom microcontrollers
PCF84C41A Telecom microcontrollers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCF5083H/001/F2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF5083H/5V2/F3 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF5083H/F2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF51AC128ACFUE 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
PCF51AC128ACLKE 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*