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參數(shù)資料
| 型號(hào)： | PCF5083 |
| 廠(chǎng)商： | NXP Semiconductors N.V. |
| 英文描述： | STEEL COVER |
| 中文描述： | GSM信號(hào)處理IC |
| 文件頁(yè)數(shù)： | 12/136頁(yè) |
| 文件大小： | 602K |
| 代理商： | PCF5083 |
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1996 Oct 29
12
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
Equalization for normal and synchronization bursts
Power measurement of serving and neighbouring cells
Tone and side-tone generation.
2.5 kbytes of RAM are free for downloading of additional
software modules e.g. rate adaptation, handsfree, voice
recognition.
The DSP communicates via two serial ports to the
baseband interface IC and to the IOM
-2 Interface and
Voice Port for speech and data transmission. For
command and data transfer it is connected to a
microcontroller via its 8-bit Host Port and the
68000 compatible Host Interface. The I/O port of the DSP
core provides four general purpose I/O lines. Some of the
port lines are used as dedicated control signals.
The Timer and Interface functions include a GSM specific
hardware timer and a couple of interface functions which
simplify system design and keep the chip count to a
minimum.
The Timing Generator provides the TDMA burst timing and
power on/off signals for the RF transmitter, RF receiver,
synthesizer, DSP and baseband interface IC. The timing
signals can be programmed with an accuracy of a
quarterbit (
1
500
TDMA frame). Their output polarity is
programmable.
The RF-IC Interface is used to program the RF ICs and the
synthesizer. It is compatible with the Philips ‘Three Wire
Bus’ and other standards. The bus consists of clock, data
and several enable lines to transfer data between the
PCF5083 and the connected devices. ICs of one family
share the same enable line. Their unique address is a part
of the data stream. ICs of different families use separate
enable lines.
The PCF5083 includes an IOM
-2 Interface to connect
external accessories e.g. a handsfree set. It may be used
as a software download interface and provides access for
the Digital Audio Interface during Type Approval.
The Audio Interface provides the connection between a
local codec, the IOM
-2 Bus and the DSP.
The ON/OFF Logic performs the basic power-up and
power-down switching function for the whole mobile. It
controls the supply voltage switches for the terminal. The
on/off conditions are controlled via the operators
keyboard, a low voltage battery indication circuit, the
Watchdog Timer or an auxiliary switch on input for general
purpose use.
The man-machine interface section includes a dedicated
RS232 interface and generates a 13 MHz clock for the
keyboard and card reader controller. If this controller is
inactive, the clock is stopped to save power. If the
controller requests service, the clock is switched on again.
The PCF5083 includes a 6-bit general purpose parallel
port to control system functions. One bit of the port is used
on-chip to provide a reset signal for the DSP core.
The PCF5083 is accessed via its 8-bit, 68000 compatible
Host Interface. Separate chip enable lines for the DSP and
the Timer core are available. The DSP core provides a
signal to be used as DTACK for maximum speed
operation. Three interrupt lines are provided for the
microcontroller.
The PCF5083 requires two clock signals. The 13 MHz
main clock is used internally to generate the TDMA timing
and as a reference clock for the on-chip PLL. A second
clock of 32.768 kHz is used for a real time clock/calendar,
a Watchdog Timer and to provide timing in a power
reducing Sleep mode. During this mode TDMA timing is
maintained with slow running, high accuracy counters,
while all timing signals are kept inactive to save power.
The on-chip PLL generates three clocks (13, 39 and
52 MHz) which are manipulated to generate the internal
DSP clock (19.5 MHz), a 19.5 MHz output (CLK20M) and
a 26 MHz output (CLK26M, only version 3) used by the
microcontroller and other system components. The
13 MHz PLL output is used by the Timing Generator in
addition to being fed back to the PLL. The nominal duty
cycle of the PLL outputs is 50%, independent of the
reference clock characteristics. The PLL clock outputs
may be used for all system components requiring a
symmetric input clock therefore leading to reduced
tolerance requirements for the duty cycle of the reference
clock.
Other ICs of the Philips second generation GSM chipset
are:
P90CL301: 16-bit 68000 compatible microcontroller
TDA8005: SIM/MMI-Controller
PCF5072: Baseband Interface and Audio Codec
SA1638: IF processing IC
SA1620: RF processing IC (900 MHz)
UMA1019: Synthesizer
PCF5075: Power amplifier controller
BGY20x: UHF Power Amplifier Module family.
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| PCF84C12A | 8-BIT MICROCONTROLLER |
| PCF84C12AP | 8-BIT MICROCONTROLLER |
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| PCF84C21A | Telecom microcontrollers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF5083H/001/F2 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/5V2/F3 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/F2 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF51AC128ACFUE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| PCF51AC128ACLKE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
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