參數(shù)資料
型號： PCF5083
廠商： NXP Semiconductors N.V.
英文描述： STEEL COVER
中文描述： GSM信號處理IC
文件頁數(shù)： 115/136頁
文件大小： 602K
代理商： PCF5083
1996 Oct 29
115
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
13 TEST AND EMULATION MODES
The PCF5083 supports two test and emulation modes which make all internal signals of the DSP or Timer core externally
available. These test modes are selected with either DSPEN = 1 and TIMEN = 0, or DSPEN = 0 and TIMEN = 1.
More information on these test modes will be made available with application notes. Ask your local sales office about the
status of these application notes.
14 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1.
Stresses above those listed under Maximum Absolute Ratings may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other condition above those indicated in
the operation section of this specification is not implied.
For operating at elevated temperatures the device must be derated based on 125
°
C maximum junction temperature.
This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects
of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any
voltage larger than the rated maxima.
2.
3.
15 DC CHARACTERISTICS
T
amb
=
40 to +85
°
C; V
DD
= 3.3 V
±
10%.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DD
V
I
I
I
P
tot
T
stg
T
amb
supply voltage
input voltage on any pin with respect to ground (V
SS)
)
sink current into any pin
total power dissipation
storage temperature
operating ambient temperature
0.5
0.5
20
65
40
+5.0
V
DD
+ 0.5V
+20
800
+150
+85
V
V
mA
mW
°
C
°
C
SYMBOL
PARAMETER
(1)
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
I
DD
operating supply voltage
operating supply current
2.7
3.0
3.6
V
all sections operating;
Timer active, DSP encoding
speech; note 2
I
(VDD2)
+ I
(VDDPLL)
I
(VDD1)
I
(VDD2)
+ I
(VDDPLL)
+ I
(VDD1)
supply current Sleep mode
40
8
48
50
mA
mA
mA
note 3
I
DDtot
I
DD(SLP)
Timer sleeping, DSP
inactive
I
(VDD2)
+ I
(VDDPLL)
I
(VDD1)
I
(VDD2)
+ I
(VDDPLL)
+ I
(VDD1)
250
340
590
500
μ
A
μ
A
μ
A
note 3
I
DD(SLP)tot
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