參數(shù)資料
型號(hào): PCF5083
廠商: NXP Semiconductors N.V.
英文描述: STEEL COVER
中文描述: GSM信號(hào)處理IC
文件頁(yè)數(shù): 29/136頁(yè)
文件大?。?/td> 602K
代理商: PCF5083
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)當(dāng)前第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)
1996 Oct 29
29
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
During the three level measurement mode the burst length
of the receive burst during the TX slot is defined by the
same register RXBURSTx_REG as used for the
MON burst. The receive frequency must be set by
programming the TX channel of the RF_IC interface.
For a certain operation mode in frame N, the Timing
Generator has to be programmed with all necessary
parameters in frame N
1. For this purpose the registers
RXSTART_REG, TXSTART_REG, MONSTART_REG
and MODEx_REG have an additional pipelining stage.
The pipelining takes place at the beginning of every TDMA
frame with the frame interrupt generation.
8.3.3
S
LEEP MODE
The Sleep mode circuitry is used to reduce the power
consumption during the Idle mode. During Sleep mode,
the mobile is switched on, but no call is active. The mobile
is only activated to read the paging blocks and for
neighbour cell monitoring. Outside these intervals, all ICs
can be switched off to save power.
In this mode also the main 13 MHz oscillator may be
switched off. To maintain TDMA timing alignment, the
PCF5083 is running temporarily on a slower clock
frequency, derived from the 32.768 kHz real time clock
oscillator. This clock is called Sleep Clock (SLCLK).
During the Sleep mode the PCF5083 controls the signals
specified in Table 15, the timing for these signals is
detailed in Table 16.
Sleep mode is activated with
QBCCTRL_REG[SLEEP] = 1 and
QBCCTRL_REG[SLEEPRED] = 0 (the SLEEPRED flag is
used for reduced Sleep mode, see below). The register
SLEEPCNT_REG has to be programmed with the number
of TDMA frames the mobile wants to sleep minus one.
Register FRAMECNT_REG is automatically cleared when
the Sleep mode is entered and counts the number of
TDMA frames actually slept. The 9-bit registers
SLEEPCNT_REG and FRAMECNT_REG allow a
maximum Sleep mode period of 512 frames. Refer to
Fig.11 for the signal flow.
Table 15
Signals controlled by the PCF5083 during Sleep mode
Table 16
Sleep mode signal timing
Notes
1.
(N)REFON is not deactivated if the Sleep mode is initiated while the sleep clock calibration procedure is running (see
Section 8.3.3.3), while the IOM
-2 interface is enabled or the MMICLK flag in register HWCTRL_REG is set,
indicating that the MMI controller requires the 13 MHz clock.
Maximum 295 ms before Sleep mode terminates with 4.6 ms resolution {[(0 to 63) + 1]
×
4.6 ms}.
2.
SIGNAL
DESCRIPTION
REFON
NREFON
DSPON
GPON1
GPON2
Reference oscillator on. Active HIGH output.
Inverted REFON output.
DSP power-down (connected on chip).
General purpose power-down and radio part interface 3-state enable. Active HIGH output.
General purpose power-down. Active HIGH output.
SIGNAL
FRAME NUMBER
ACTIVATION OF SIGNAL IF
SLEEPCNT_REG EQUALS
(N)REFON
DSPON
GPON1
GPON2
In frame N + 1 on the third positive SLCLK edge
In frame N + 1 on the second positive SLCLK edge
In frame N + 1 on the second positive SLCLK edge
In frame N + 1 on the third positive SLCLK edge
REFON_REG (notes 1 and 2)
KISSON_REG (note 2)
GPON1_REG (note 2)
GPON2_REG (note 2)
相關(guān)PDF資料
PDF描述
PCF84C12A 8-BIT MICROCONTROLLER
PCF84C12AP 8-BIT MICROCONTROLLER
PCF84C12AT 8-BIT MICROCONTROLLER
PCF84C21A Telecom microcontrollers
PCF84C41A Telecom microcontrollers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCF5083H/001/F2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF5083H/5V2/F3 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF5083H/F2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF51AC128ACFUE 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
PCF51AC128ACLKE 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT