參數(shù)資料
型號： PCF5083
廠商： NXP Semiconductors N.V.
英文描述： STEEL COVER
中文描述： GSM信號處理IC
文件頁數(shù)： 33/136頁
文件大?。?/td> 602K
代理商： PCF5083
1996 Oct 29
33
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
8.4
RF-IC Interface Bus
This block provides a serial interface to control the RF
devices like synthesizer, baseband interface IC etc. The
interface is upward compatible with the ‘Philips Three Wire
Bus’. Compared with the Philips bus it is extended for
bidirectional data transfer and additional timing modes are
implemented. The interface consists of a clock (RFCLK), a
data output (RFDO), a data input (RFDI) and enable lines
(RFEN1 to RFEN4 and RFE). The interface is subdivided
into three logical channels as described below.
8.4.1
F
REQUENCY
S
ETTING
C
HANNEL
The registers RX_REG, TX_REG and MON_REG are set
up during frame N
1 with the frequency information for
the RX, TX or MON burst of frame N. Therefore these
three registers have a pipeline stage. The pipelining takes
place at the beginning of every TDMA frame together with
the frame interrupt generation. The transmission of the
three registers is controlled from the timing generator as
described in Section 8.3.2.7. The register TX_REG is also
used for a monitor burst during the TX timeslot. The
register RFCTRL0_REG contains four address bits
(A0 to A3) which are transmitted with either of the three
data registers. The data structure and the function of the
mode (M0 to M2) and select (SEL0, SEL1) flags contained
in RFCTRL0_REG is described in Section 8.4.4.
8.4.2
G
AIN
C
ONTROL
C
HANNEL
The registers RXGAIN_REG, TXGAIN_REG and
MONGAIN_REG are set up during frame N
1 with the
gain control information for the RX burst or MON burst of
frame N. Therefore these three registers have a pipeline
stage. The pipelining takes place at the beginning of every
TDMA frame together with the frame interrupt generation.
The transmission of the three registers is controlled from
the timing generator as described in Section 8.3.2.7. No
gain information is sent prior to a TX-burst. The register
TXGAIN_REG is used for a monitor burst during the TX
timeslot. The DAC bit of these registers is not transmitted
but used to select between the registers DAC0_REG and
DAC1_REG. The register RFCTRL1_REG contains four
address bits (A0 to A3) which are transmitted with either of
the three data registers. The data structure and the
function of the mode (M0 to M2) and select
(SEL0 and SEL1) flags contained in RFCTRL1_REG is
described in Section 8.4.4.
The DAC flag in xxGAIN_REG selects either DAC0_REG
or DAC1_REG to be transmitted immediately after
xxGAIN_REG. These two registers hold static data and do
not have an additional frame pipeline stage like the
xx_REG or xxGAIN_REG. The contents of register
RFCTRL2_REG functionally corresponds to the contents
of RFCTRL1_REG.
Two further registers, DACON_REG and DACOFF_REG
exist. They are used to power-up or power-down a gain
setting DAC. These two registers also hold static data like
DACx_REG. The transmission of the three registers is
controlled from the timing generator as described in
Section 8.3.2.7. The contents of RFCTRL3_REG register
functionally corresponds to the contents of
RFCTRL1_REG or RFCTRL2_REG.
The MSB (bit 16) of the registers DAC0_REG,
DAC1_REG, DACON_REG and DACOFF_REG is located
in register MSB_REG, because of the limited address
space.
8.4.3
I
MMEDIATE
C
ONTROL
C
HANNEL
The Immediate Control Channel (IMC) consists of the
registers IMCOUT_REG for the output direction and
IMCIN_REG for the input direction. The contents of
IMCOUT_REG are transmitted every time a new data
word is written to it. The flag SIINT_REG[IMC_OBE] is set
after the contents of IMCOUT_REG was copied to the shift
register. If the corresponding mask flag
SIMASK_REG[IMC_OBE_MASK] is set, the serial
interface interrupt SI_INT is activated. Together with
IMCOUT_REG being transmitted, the data at RFDI is read
into register IMCIN_REG. The flag SIINT_REG[IMC_IBF]
is set at the end of the shift operation. The interrupt
handling corresponds to the IMC_OBE flag. The interrupt
flags are cleared when their corresponding register is
written respectively read.
The mode flags in IMCOUT_REG have the same function
as the flags in RFCTRLx_REG. The four select flags
(SEL0 to SEL3) correspond to the enable lines
RFEN1 to RFEN4. Each enable line is activated if their
corresponding select flag is set. Therefore it is possible to
activate more than one line at a time.
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相關代理商/技術參數(shù)
參數(shù)描述
PCF5083H/001/F2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF5083H/5V2/F3 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF5083H/F2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC
PCF51AC128ACFUE 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT
PCF51AC128ACLKE 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT
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