參數(shù)資料
型號: PCF5083
廠商: NXP Semiconductors N.V.
英文描述: STEEL COVER
中文描述: GSM信號處理IC
文件頁數(shù): 34/136頁
文件大?。?/td> 602K
代理商: PCF5083
1996 Oct 29
34
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
Table 17
Select flags in register IMCOUT_REG
The inhibit flag (INH) in IMCOUT_REG controls whether
the IMC operation is inhibited during a receive or transmit
burst indicated with PDRX2 or NPDTX2 active. If the INH
flag is set the IMC operation is delayed until PDRX2 and
NPDTX2 become inactive. If the INH flag is reset the two
lines are don’t care.
8.4.4
O
PERATION
M
ODES AND
C
ONTROL
R
EGISTERS
The characteristics of each channel are controlled using
the contents of the registers RFCTRL0_REG to
RFCTRL3_REG.
The interface is programmable, one of three timing modes
can be selected for every data transfer. For the exact
timing see Chapter 16. In Mode 3 the transmission of the
data registers associated with the control register is
disabled.
If there is a conflict between the different data channels,
data transmission is scheduled according to Table 22.
Table 18
RC-IF Interface Bus Control Registers
SEL0 SEL1 SEL2 SEL3
ACTIVE ENABLE LINE
1
X
X
X
X
1
x
X
X
X
1
X
X
X
X
1
RFSEN1
RFSEN2
RFSEN3
RFSEN4
BIT
FLAG
OPERATION
7
6
5
4
M1
M0
SEL1
SEL0
These two bits select the timing
mode, see Table 19.
These two bits are used to assert
the enable lines RFEN1 to RFEN1,
see Table 21.
These four bits form the address
field.
3
2
1
0
A3
A2
A1
A0
Table 19
Selection of the RC-IF Interface timing modes
Note
1.
The 16 or 21 data bits are transmitted MSB first
according to Table 20.
Table 20
RF-IC Interface data structure
Note
1.
The 21 bits consist of D17 to D0 and A2 to A0.
Table 21
Selection of enable lines RFEN1 to RFEN4
Table 22
Order of priority
MODE
M1
M0
BITS
TRANSFERRED
RFE
ASSERTED
0
1
2
3
0
0
1
1
0
1
0
1
21
21
16
no
no
yes
Transmission of the corresponding
data registers is disabled.
MODE
BITS
TRANSFERRED
21
(1)
21
16
1ST BIT
LAST
BIT
0 and 1
IMC channel
2
D17
D20
D15
A0
D0
D0
SEL1
SEL0
ENABLE LINE ASSERTED
0
0
1
1
0
1
0
1
RFEN1
RFEN2
RFEN3
RFEN4
PRIORITY
TRANSMISSION
Highest
frequency setting
gain control DACOFF_REG
gain control DACON_REG
gain control xxGAIN_REG then
DACx_REG
Immediate Control Channel
Lowest
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