參數(shù)資料
型號: PCF5083
廠商: NXP Semiconductors N.V.
英文描述: STEEL COVER
中文描述: GSM信號處理IC
文件頁數(shù): 103/136頁
文件大?。?/td> 602K
代理商: PCF5083
1996 Oct 29
103
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
Table 80
Bit mask register (Power-Down Control Lines)
Note
1.
RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘
’ denotes not affected from reset line.
During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other
registers are undefined and have to be set by the controller.
Table 81
Quarterbit Counter Control Register
Note
1.
RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘
’ denotes not affected from reset line.
During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other
registers are undefined and have to be set by the controller.
BIT
R/W
SYMBOL
OPERATION (if bit is set)
RST = 0
RSTx = 0
(1)
0
1
2
R/W
R/W
R/W
PDRX1
PDRX2
(N)PDTX1,
(N)PDBIAS
NPDTX2
PDSYN
TXKEY1
TXKEY2
RXON
TXON
BEN
GPON1
GPON2
REFON
DSPON
NREFON
A logic 1 enables the control line. A logic 0 disables the
control line, output level determined with corresponding
output polarity flag
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
1
1
1
1
Bit
R/W
SYMBOL
OPERATION (if bit is set)
RST = 0
RSTx = 0
(1)
0
1
2
3
4
5
6
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SYNC
INSERT
EXTRACT
SLEEP
SLEEPRED
CAL
FSCEXT
FSCRED
Enable SYNC mode
Enable INSERT mode
Enable EXTRACT mode
Enable Sleep mode
Enable Reduced Sleep mode
Start Sleep mode calibration procedure
Enable IOM
-2 FSC period extension mode
Enable IOM
-2 FSC period reduction mode
0
0
0
0
0
0
0
0
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