參數(shù)資料
型號: PCF5083
廠商: NXP Semiconductors N.V.
英文描述: STEEL COVER
中文描述: GSM信號處理IC
文件頁數(shù): 100/136頁
文件大小: 602K
代理商: PCF5083
1996 Oct 29
100
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
13
GPON2_REG
6
W
Time of GPON2 getting active in TDMA frames before the end
of the Sleep mode
Time of DSPON getting active in TDMA frames before the end
of the Sleep mode
Time of (N)REFON getting active in TDMA frames before the
end of the Sleep mode
Time of PDRX1 getting active in 32 QB before RXON active
Time of PDRX2 getting active in 32 QB before RXON active
Time of PDTX1 getting active in 32 QB before TXON active
Time of NPDTX2 getting active in 32 QB before TXON active
Time of PDBIAS getting active in 32 QB before TXON active
Time of PDSYN getting active in 32 QB before RXON/TXON
active
Time of DACON_REG to be sent in 32 QB before RXON active
PDTX1, NPDTX2 and PDSYN inactive to TXKEY1 inactive
delay in QB
TXKEY2 inactive to TXKEY1 inactive delay in QB
TXKEY2 active to TXON active delay in QB
TXKEY1 active to TXON active delay in QB
Polarity of Power-Down Control Lines; see Table 79
Bit mask register for Power-Down Control Lines; see Table 80
Quarterbit counter control register; see Table 81
Sleep quarterbit counter increment
Stop OFF-Timer with data value A5H
QBC access for synchronization
R: read 15-bit quarterbit counter (
1
4
QB resolution)
W: write 13-bit synchronization value (1 QB resolution)
Number of TDMA frames to sleep
Duration of last Sleep mode period in TDMA frames
Hardware Control Register; see Table 82
Real Time Clock registers; see Table 83
RF Bus: RX frequency
RF Bus: TX frequency
RF Bus: MON frequency
RF Bus: RX gain
RF Bus: Gain setting for a MON burst during the TX timeslot
14
15
reserved
DSPON_REG
6
W
16
REFON_REG
6
W
17
18
19
1A
1B
1C
PDRX1_REG
PDRX2_REG
PDTX1_REG
PDTX2_REG
PDBIAS_REG
PDSYN_REG
5
5
W
W
W
W
W
W
1D
1E
AGCSTART_REG
PDDELAY_REG
W
W
6
1F
20, 21
22, 23
24, 25
26, 27
28
29
KEYOFF_REG
KEYON2_REG
KEYON1_REG
POL_REG
MASK_REG
QBCCTRL_REG
SQBCINC_REG
STOP_REG
QBC_REG
6
9
9
W
W
W
14
15
8
8
8
15
13
R/W
R/W
R/W
R
W
R
W
2A, 2B
2C, 2D
SLEEPCNT_REG
FRAMECNT_REG
HWCTRL_REG
reserved
RX_REG
reserved
TX_REG
reserved
MON_REG
reserved
RXGAIN_REG
reserved
TXGAIN_REG
9
9
11
17
17
17
18
18
W
R
2E, 2F
30 to 3F
3E
3F to 41
42
43 to 45
46
47. to 49
4A
4B to 4D
4E
4F to 51
R/W
R/W
W
W
W
W
W
OFFSET
REGISTER
SIZE
R/W
(1)
DESCRIPTION
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