參數(shù)資料
型號: PCF5083
廠商: NXP Semiconductors N.V.
英文描述: STEEL COVER
中文描述: GSM信號處理IC
文件頁數(shù): 121/136頁
文件大?。?/td> 602K
代理商: PCF5083
1996 Oct 29
121
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
Notes to the AC characteristics
1.
Parameters are valid over the specified temperature range.
2.
All voltages are measured with respect to ground (V
SS
). For testing all inputs swing between 0 V and V
DD
with a
transition time of 4 ns. All time measurements are made with input voltages of 0 V and V
DD
and output voltages of
0.2
VDD
and 0.8V
DD
as appropriate.
3.
Test conditions for outputs: C
L
= 40 pF, except open-drain outputs. Test conditions for open-drain outputs:
C
L
= 40 pF; I
L
= 1.8 mA at V
DD
.
4.
All timing diagrams should only be referred to in regard to the edge-to-edge measurements of the timing
specifications. They are not intended as a functional description of the input and output signals. Refer to the
functional description and related timing diagrams for device operation. All setup and hold times are specified with
respect to V
IH
and V
IL
. All delay times with respect to 0.5V
DD
. Times with only typical values are not tested during IC
production
5.
For testing the AC characteristics, the low swing input CKI is driven with a square wave signal of the specified
minimum peak-to-peak input voltage swing. The typical values for additional components are: C1 = 4.7 nF,
C
2
= 100 pF and R
1
= 10 k
.
6.
For testing the AC characteristics, the input CLK32I is driven with a standard test signal (see note 2). A typical
application for crystal operation is: R = 10 M
, fQ = 32.768 kHz, C
1
= 15 pF, C
T
= 15 pF (for crystal C
L
= 12.5 pF).
7.
These times are guaranteed by design and are not tested during IC production.
8.
DCLK internally divided-by-two to drive the DSP; t
DCLKOUT
=
1
DCLK.
9.
This time specified is when PI is empty.
10. This time specified is when PO is full.
11. Not tested in production.
12. Mode 0 and 1, or Mode 2 are selected by register settings. Refer to the functional specification.
13. The output DCL has two different cycle times depending on the DCL period number. Refer to the functional
description. The table lists the cycle times for the 1.536 MHz internal clock mode and the maximum clock frequency
in external clock mode. The minimum cycle times correspond to the 4.096 MHz external clock mode and therefore
apply to all the external clock modes.
14. The Audio Interface timing is given for the non-transparent mode. In transparent mode the IOM
-2 Interface timing
applies to the Audio Interface accordingly, refer to functional description.
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