參數(shù)資料
型號: ORT8850L-3BM680C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 87/105頁
文件大?。?/td> 0K
描述: IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告: Product Discontinuation 01/Aug/2011
標準包裝: 24
系列: *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
82
Table 35. ORT8850H Pins That Are Unused in ORT8850L
Users should avoid using these pins if they plan to migrate their ORT8850H design to an ORT8850L.
Package Pinouts
Table 36 provides the package pin and pin function for the ORT8850 FPSC and packages. The bond pad name is
identied in the PIO nomenclature used in the
ispLEVER design editor. The Bank column provides information as
to which output voltage level bank the given pin is in. The Group column provides information as to the group of
pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-
ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then
the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specic die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
BGA Ball Bonds
ORT8850H PIOs
K4
PL11A
M5
PL13A
R5
PL20A
T5
PL21A
W4
PL27A
AA2
PL28A
Y4
PL29A
AC4
PL35A
AD5
PL37A
AG1
PL38A
AP4
PB3A
AK10
PB9A
AK11
PB10A
AM9
PB11A
AN9
PB12A
AM14
PB19A
AN14
PB20A
D11
PT12A
E13
PT11A
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