參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 15/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
17
STM Macrocells - Overview
The Synchronous Transport Module (STM) portion of the embedded core consists of two quads, STM A and B. The
STM macrocells provide transmitter and receiver logic blocks on a per SERDES basis channel and are located in
the data path between the FPGA interface and the HSI macrocell. The STM macrocells' main functions are framing
and aligning data into standard STS-N frames as well as providing a 1's density through scrambling/descrambling.
Figure 7. STM Macrocell Partitioning
Transmit STM Macrocell Logic - Overview
In the transmit direction (FPGA interface to the backplane), each STM macrocell will receive frame aligned streams
of STS-12 data (maximum of four streams) from the FPGA logic. The transmitter receive data interface is in a par-
allel 8-bit format. A common frame pulse for all 8 channels is provided as an input from the FPGA logic to the trans-
mit SONET block.
On each frame pulse the A1/A2 frame alignment bytes are inserted into the data stream and will overwrite any data
in this location of the frame. TOH data can be optionally inserted into the transmitted SONET frame. The SONET
frame is then optionally scrambled and sent to the HSI macrocell.
TOH data can be inserted into the transmit data stream in two ways; transparently or by inserting serial TOH data
from a TOH serial interface signal in the FPGA logic. In the transparent mode, the SPE and TOH data received on
parallel input bus is transferred, unaltered, to the serial LVDS output. However, B1 byte of STS-1 is always replaced
with a new calculated value (the 11 bytes following B1 are replaced with all zeros). Likewise, in serial and transport
mode A1 and A2 bytes of all STS-1s are always regenerated. In the TOH serial insertion mode the SPE bytes are
transferred unaltered from the input parallel bus to the serial LVDS output. TOH bytes, however, are received from
the FPGA logic through the serial input port and are inserted in the STS- 12 frame before being sent to the LVDS
FPGA
Logic
I/O DEMUX
and
LVDS
Buffers
TXDxx_W_[P:N]
TXDxx_P_[P:N]
Note: xx = AA, ...
RXDxx_W_[P:N]
RXDxx_P_[P:N]
SYS_CLK_[P:N]
System Clock
RX Serial DataAA
TX Serial DataAA
RX Serial DataAB
TX Serial DataAB
RX Serial DataAC
TX Serial DataAC
RX Serial DataAD
TX Serial DataAD
RX Serial DataBA
TX Serial DataBA
RX Serial DataBB
TX Serial DataBB
RX Serial DataBC
TX Serial DataBC
RX Serial DataBD
TX Serial DataBD
Common Signals
Quad B
Quad A
FPGA_SYSCLK
SYS_FP
DOUTAA[7:0]
DINAA[7:0]
DOUTAB[7:0]
DINAB[7:0]
DOUTAC[7:0]
DINAC[7:0]
DOUTAD[7:0]
DINAD[7:0]
DOUTBA[7:0]
DINBA[7:0]
DOUTBB[7:0]
DINBB[7:0]
DOUTBC[7:0]
DINBC[7:0]
DOUTBD[7:0]
DINBD[7:0]
STM Macrocell
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
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參數(shù)描述
ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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