- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1958 > ORT8850L-3BM680C (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 8CH 680-BGA PDF資料下載
參數(shù)資料
| 型號： | ORT8850L-3BM680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 59/105頁 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當(dāng)前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁
Lattice Semiconductor
ORCA ORT8850 Data Sheet
57
For software control of the LVDS protection switching there is an enable bit to enable software control, and a bit per
channel which selects main or protect. The enable register is at 0x30008 in the memory map (Table 19).
Memory Map
The memory map for the ORT8850 core is only part of the full memory map of the ORT8850 device. The ORT8850
is an ORCA Series4 based device and thus uses the system bus as a communication bridge. The ORT8850 core
register map contained in this data sheet only covers the embedded ASIC core of the device, not the entire device.
The system bus itself, and the generic FPGA memory map, are fully documented in the MPI/System Bus Applica-
tion Note. As part of the system bus, the embedded ASIC core of an FPSC is located at address offset 0x30000.
The ORT8850 embedded core is an eight-bit slave interface on the Series 4 system bus.
Each ORCA device contains a device ID. This device ID is unique to each ORCA device and can be used for device
identication and assist in system debugging. The device ID is located at absolute address 0x00000 - 0x00003.
The ORT8850H’s device ID is 0xDC0123C0 and the ORT8850L’s device ID is 0xDC0121C0. More information on
the device ID and other Series 4 generic registers can be found in the MPI/System Bus Application Note.
The ORT8850 core registers are clocked by the reference clock SYS_CLK_P/N. If a clock is not provided to the ref-
erence clock, the registers will fail to operate.
The ORT8850 core registers do not check for parity on a write operation. On a read operation, no parity is gener-
ated, and a “0” is passed back to the initiating bus master interface on the parity signal line.
Registers Access and General Description
The memory map comprises three address blocks:
Generic register block: ID, revision, scratch pad, lock and reset register.
Device register block: control and status bits, common to the eight channels in each of the two quad interfaces.
Channel register blocks: each of the four channels in both quads have an address block. The four address blocks
in both quads have the same structure, with a constant address offset between channel register blocks.
All registers are write-protected by the lock register, except for the scratch pad register. The lock register is a 16-bit
read/write register. Write access is given to registers only when the key value 0x0580 is present in the lock register.
An error ag will be set upon detecting a write access when write permission is denied. The default value is
0x0000.
After power-up reset or soft reset, unused register bits will be read as zeros. Unused address locations are also
read as zeros. Bit in write-only registers will always be read as zeros.
This table is constructed to show the correct values when read and written via the system bus MPI interface. When
using this table while interfacing with the system bus user logic master interface, the data values will need
to be byte ipped. This is due to the opposite orientation of the MPI and master interface bus ordering. More infor-
mation on this can be found in the MPI/System Bus Application Note (TN1017).
LVDS_PROT_BA
Channel BA gets TXD_BA_W_[P:N]
Channel BA gets TXD_BA_P_[P:N]
LVDS_PROT_BB
Channel BB gets TXD_BB_W_[P:N]
Channel BB gets TXD_BB_P_[P:N]
LVDS_PROT_BC
Channel BC gets TXD_BC_W_[P:N]
Channel BC gets TXD_BC_P_[P:N]
LVDS_PROT_BD
Channel BD gets TXD_BD_W_[P:N]
Channel BD gets TXD_BD_P_[P:N]
Table 18. LVDS Protection Switching (Continued)
FPGA Interface Signal
When ‘0’
When ‘1’
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P1010PSE5HFA | MPU PROTO 800/667 425-TEPBGA1 |
| P1013NXN2LFB | IC MPU 1067MHZ 689TEPBGA |
| P1013PSE2EFA | IC MPU PROTO 600MHZ 689-TEPBGA |
| P1014NSN5DFA | IC MPU 800MHZ 425TEPBGA1 |
| P1014NSN5FFA | IC MPU 800MHZ 425TEPBGA1 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850L-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。