- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1958 > ORT8850L-3BM680C (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 8CH 680-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ORT8850L-3BM680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 83/105頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁當(dāng)前第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁
Lattice Semiconductor
ORCA ORT8850 Data Sheet
79
MPI_BDIP
I
MPI_BDIP is driven by the
PowerPC processor in MPI mode. Assertion of this pin indicates that the
second beat in front of the current one is requested by the master. Negated before the burst transfer
ends to abort the burst data phase.
MPI_TSZ[0:1]
I
MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer size for
the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
A[21:0]
O
During master parallel mode A[21:0] address the conguration EPROMs up to 4M bytes.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.*
MPI_ACK
O
In
MPI mode this is driven low indicating the MPI received the data on the write cycle or returned
data on a read cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.*
MPI_CLK
I
This is the
PowerPC synchronous, positive-edge bus clock used for the
MPI interface. It can be a
source of the clock for the embedded system bus. If MPI is used this will be the
AMBA bus clock.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.*
MPI_TEA
O
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the inter-
nal system bus for the current transaction.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.*
MPI_RTRY
O
This pin requests the MPC860 to relinquish the bus and retry the cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after conguration.*
D[0:31]
I/O
Selectable data bus width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write trans-
action and driven by MPI in a read transaction.
I
D[7:0] receive conguration data during master parallel, peripheral, and slave parallel conguration
modes when WR is low and each pin has a pull-up enabled. During serial conguration modes, D0
is the DIN input.
O
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
I/O After conguration, if MPI is not used, the pins are user-programmable I/O pins.*
DP[0:3]
I/O
Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15], DP[2]
for D[16:23], and DP[3] for D[24:31].
After conguration, if MPI is not used, the pins are user-programmable I/O pin.*
DIN
I
During slave serial or master serial conguration modes, DIN accepts serial conguration data syn-
chronous with CCLK. During parallel conguration modes, DIN is the D0 input. During conguration,
a pull-up is enabled.
I/O After conguration, this pin is a user-programmable I/O pin.*
DOUT
O
During conguration, DOUT is the serial data output that can drive the DIN of daisy-chained slave
devices. Data out on DOUT changes on the rising edge of CCLK.
I/O After conguration, DOUT is a user-programmable I/O pin.*
TESTCFG
I
During conguration this pin should be held high, to allow conguration to occur. A pull up is
enabled during conguration.
I/O After conguration, TESTCFG is a user programmable I/O pin.*
LVDS_R
— Reference resistor connection for controlled impedance termination of Series 4 FPGA LVDS inputs.
Table 32. FPGA Common-Function Pin Descriptions (Continued)
Symbol
I/O
Description
1. The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other conguration pins (and the activa-
tion of all user I/Os) is controlled by a second set of options.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P1010PSE5HFA | MPU PROTO 800/667 425-TEPBGA1 |
| P1013NXN2LFB | IC MPU 1067MHZ 689TEPBGA |
| P1013PSE2EFA | IC MPU PROTO 600MHZ 689-TEPBGA |
| P1014NSN5DFA | IC MPU 800MHZ 425TEPBGA1 |
| P1014NSN5FFA | IC MPU 800MHZ 425TEPBGA1 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850L-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。