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| 型號： | ORT8850L-3BM680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 60/105頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
58
Table 19. Memory Map Descriptions
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description
30000
[0:7]
R
-
05
Internal device revision
30001
[0:7]
R
-
80
Internal device revision
30002
[0:7]
R
-
80
Internal device revision
30003
[0:7]
R/W
scratch pad
00
The scratch pad has no function and is not used anywhere in
the core. However, this register can be written to and read from
for debugging purposes.
30004
[0:7]
R/W
lockreg MSB
00
In order to write to registers in memory locations 0x30006 to
0x300FF, lockreg MSB and lockreg LSB must be respectively
set to the values of 05 and 80. If the MSB and LSB lockreg val-
ues are not set to {05, 80}, then any values written to the regis-
ters in memory locations 0x30006 to 0x300FF will be ignored.
After reset (both hard and soft), the core is in a write locked
mode. The core needs to be unlocked before it can be written
to.
Also note that the scratch pad register (0 x 30003) can always
be written to as it is unaffected by write lock mode.
30005
[0:7]
R/W
lockreg LSB
00
30006
[0]
R/W
global reset
0
The global reset is a soft (software initiated) reset which will
have the exact reset effect as a hard (RST_N pin) reset.This is
a pulse register and does not have to be cleared.
[1-7]
-
Not Used
0
30007
[0:7]
-
Not Used
00
Device Register Blocks
30008
[0]
R/W
LVDS loopback
control
0
0 = No Loopback
1 = LVDS loopback, transmit to receive. TX serial data is looped
back to the RX serial input. TX data is still available at the TX
pins
[1]
-
Not Used
0
[2]
-
Not Used
0
[3]
R/W
LVDS Protection
Switch enable
0
0 = Protection switching performed via bit settings in registers
0x30037 etc.
1 = Protection switching performed via hardware pins
LVDS_PROT_SWITCH_xx
[4]
R/W
TOH RX serial
enable
0
TOH_CK_FP_EN signal
[5-7]
-
Not Used
0
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| ORT8850L-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
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