參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 11/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
13
Figure 3. Top Level Block Diagram ORT8850 Embedded Core SONET Logic Block Common Signals and
Channel AA Data Flow
Each quad can frame independently in STS-3, STS-12 or STS-48 format. If using STS-48 format all channels in the
quad will be used and be treated as a single STS-48 channel using the quad STS-12 format in which each inde-
pendent channel carries entire STS-12 frames. The byte order for STS-48 must be created by the designer in the
FPGA design. Note that the recovered data will always continue to be in the same order as transmitted data.
Each channel contains transmit path and receive path logic, both of which are organized around High Speed Inter-
connect (HSI) and Synchronous Transport Mode (STM) macrocells. Additional logic allows insertion and extraction
of information in the Transport Overhead area of the SONET frame. (Support for loopback and for switching
between redundant serial links is also provided but is not shown in Figure 3). The following sections will give an
overview of the pseudo-SONET protocol supported by the ORT8850 and a top level overview of the Synchronous
Transport Module (STM) and High Speed Interconnect (HSI) macrocells, which provide the SONET functionality.
*TX_TOH_CK_EN
*TOH_InAA
FPGA
Logic
Common Signals
Receive, Ch. AA
Channel AB
Channel BD
.
4:1 MUX
(x8)
Transmit, Ch. AA
TOH Functions, Ch. AA
FPGA_SYSCLK
SYS_FP
LINE_FP
*TOH_CLK
*RX_TOH_CK_EN
*RX_TOH_FP
*TOH_CK_LP_EN
*TOH_OUTAA
*TOH_AA _EN
DOUTAA [7:0]
DOUTAA _PAR
DOUTAA _FP
DOUTAA _SPE
DOUTAA _C1J1
DOUTAA _EN
CDR_CLK_AA
DINAA[7:0]
DINAA_PAR
TX STM Block
RX HSI Block
TOH Insertion Block
Note: xx = AA, ..., BD
TOH Extraction
Block
Note: Signals
marked with
asterisk only
used in TOH
Insert Mode
TX HSI Block
Pointer
Processing
Multi-
Channel
Align
RX STM Block
Descrambler
System
Clock
RX Serial
Data
TX Serial
Data
TXDxx_W_[P:N]
TXDxx_P_[P:N]
RXDxx_W_[P:N]
RXDxx_P_[P:N]
I/O MUX,
I/O DEMUX
and
LVDS
Buffers
SONET Logic Blocks
SYS_CLK_[P:N]
Signals
on
Package
Pins
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