參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 76/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
72
Table 25. Channel Output Jitter (622 Mbits/s)
Table 26. Channel Output Jitter (155 Mbits/s)
Table 27. Synthesizer Specications
Parameter
Conditions
Min.
Typ.
1
Max.
1
Units
Deterministic
—
0.09
0.10
UIp-p
Random
—
0.11
0.14
UIp-p
Total
2,3
—
0.20
0.24
UIp-p
1. With PRBS 2^7 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., 0°C to 85°C, 1.425 V to 1.575 V supply.
2. Wavecrest SIA-3000 instrument used to measure one-sigma (rms) random jitter component value. This value is multiplied by 14 to provide
the peak-to-peak value that corresponds to a BER of 10
-12.
3. Total jitter measurement performed with Wavecrest SIA-3000 at a BER of 10
-12. See instrument documentation and other Wavecrest publi-
cations for a detailed discussion of jitter types included in this measurement.
Parameter
Conditions
Min.
Typ.
1
Max.
1
Units
Deterministic
—
0.027
0.035
UIp-p
Random
—
0.053
0.065
UIp-p
Total
2,3
—
0.08
0.10
UIp-p
1. With PRBS 2^7 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., 0°C to 85°C, 1.425 V to 1.575 V supply.
2. Wavecrest SIA-3000 instrument used to measure one-sigma (rms) random jitter component value. This value is multiplied by 14 to provide
the peak-to-peak value that corresponds to a BER of 10
-12.
3. Total jitter measurement performed with Wavecrest SIA-3000 at a BER of 10
-12. See instrument documentation and other Wavecrest publi-
cations for a detailed discussion of jitter types included in this measurement.
Parameter
Conditions
Min
Typical
Max
Unit
PLL
1
Loop Bandwidth
—
6
MHz
Jitter Peaking
—
2
dB
power-up Reset Time
—
10
—
μs
Lock Acquisition Time
—
1
ms
Input Reference Clock
Frequency
—
62.5
—
106.25
MHz
Frequency Deviation
2
—
-350
—
350
ppm
Phase Change
Over a 200 ns time interval
3
—
100
ps
1. External 10 k
Ω resistor to analog ground required.
2. The frequency deviation allowed between the transmitter reference clock and receiver reference clock on a given link.
3. Translates to a frequency change of 500 ppm.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT9303 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
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ORT9303BL 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
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