參數(shù)資料
型號： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 48/105頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
47
FPGA/Embedded Core Interface Signals
0x30021
0x01
Channel AA in transparent mode
0x30039
0x01
Channel AB in transparent mode
0x30051
0x01
Channel AC in transparent mode
0x30069
0x01
Channel AD in transparent mode
0x30081
0x01
Channel BA in transparent mode
0x30099
0x01
Channel BB in transparent mode
0x300B1
0x01
Channel BC in transparent mode
0x300C8
0x01
Channel BD in transparent mode
0x30023
0x30
Channel AA - Do not insert A1/A2 or B1
0x3003B
0x30
Channel AB - Do not insert A1/A2 or B1
0x30053
0x30
Channel AC - Do not insert A1/A2 or B1
0x3006B
0x30
Channel AD - Do not insert A1/A2 or B1
0x30083
0x30
Channel BA - Do not insert A1/A2 or B1
0x3009B
0x30
Channel BB - Do not insert A1/A2 or B1
0x300B3
0x30
Channel BC - Do not insert A1/A2 or B1
0x300CB
0x30
Channel BD - Do not insert A1/A2 or B1
0x30037
0x44
Channel AA - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
0x3004F
0x44
Channel AB - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
0x30067
0x44
Channel AC - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
0x3007F
0x44
Channel AD - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
0x30097
0x44
Channel BA - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
0x300AF
0x44
Channel BB - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
0x300C7
0x44
Channel BC - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
0x300DF
0x44
Channel BD - Bypass Alignment FIFO and Pointer interpreter/mover, disable
SONET framer
Note: To select between full, half and quad rate modes, registers 0x300E1 and 0x300E2 are used. See the memory map for details on these
registers.
Table 15. FPGA/Embedded Core Interface Signals
ORT8850 FPGA/Embedded Core Interface Signals - SONET Blocks
FPGA/Embedded Core
Interface Signal Name
xx=[AA,…,BD]
Input (I) to or Output (O)
from Core
Signal Description
Common Interface Signals
FPGA_SYSCLK
O
Local reference clock from the core to the FPGA. All of the transmit
data is captured on this clock edge inside the ORT8850 core. If
using the alignment FIFO all of the parallel data from the ort8850
core will also be clocked from this clock. This signal uses an ORCA
Series4 primary clock route.
Table 14. Register Settings for Bypass Mode (Continued)
Register Address
Value
Description
相關(guān)PDF資料
PDF描述
P1010PSE5HFA MPU PROTO 800/667 425-TEPBGA1
P1013NXN2LFB IC MPU 1067MHZ 689TEPBGA
P1013PSE2EFA IC MPU PROTO 600MHZ 689-TEPBGA
P1014NSN5DFA IC MPU 800MHZ 425TEPBGA1
P1014NSN5FFA IC MPU 800MHZ 425TEPBGA1
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT9303 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
ORT9303B 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
ORT9303BL 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
ORT9303G 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*