參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 32/105頁(yè)
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
32
Figure 15. TOH Serial Port Input Framing Signals (FPGA to Core)
Although all TOH bytes from the 12 STS-1s are transferred into the device from each serial port, not all of them get
inserted in the frame. There are three hard coded exceptions to the TOH byte insertion:
Framing bytes (A1/A2 of all STS-1s) are not inserted from the serial input bus. Instead, they can always be
regenerated.
Parity byte (B1 of STS#1) is not inserted from the serial input bus. Instead, it is always recalculated (the 11 bytes
following B1 are replaced with all zeros).
Pointer bytes (H1/H2/H3 of all STS-1s) are not inserted from the serial input bus. Instead, they always ow trans-
parently from parallel input to LVDS output.
Except for the above hardcode exceptions, the source of some TOH bytes can be controlled by bits in the control
registers. The 12 STS-1 bytes forming a single STS-12 TOH header block are controlled as a whole. When cong-
ured to be in the transparent mode, the specic bytes must ow transparently from the parallel input. The 15 over-
head bytes that can be controlled on a per STS-1 basis are the following:
K1 and K2 bytes of the 12 STS-1s (24 bytes)
S1 and M0 bytes of the 12 STS-1s (24 bytes)
E1, F1, E2 bytes of the STS-1s (36 bytes)
D1 through D12 bytes of the STS-1s (144 bytes)
The C1(J0) and B2 bytes (unshaded in the following table) are also passed through transparently from the parallel
bus to the serial link.
Table 10 shows the order in which data is transferred to the serial LVDS output, starting with the most signicant bit
of the rst A1 byte. The rst bit of the rst byte is replaced by an even parity check bit over all TOH bytes from the
previous TOH frame. The source for the TOH bytes in the Serial TOH insert mode is summarized in the table.
A1 A1
A1 A2
J0
Row n-1
Row n
Etc.
B1 B1
B1 E1
F1
For
STS1
#1
For
STS1
#2
For
STS1
#12
For
STS1
#1
For
STS1
#12
. . .
Transparent Insert TOH
Data on Parallel Input Bus
SPE Data on Parallel Input Bus
Guardband of
4 TOH_CLK Cycles
Guardband of
4 TOH_CLK Cycles
Window to Send TOH Bytes
B1, E1 and F1 for all 12 STS1's
on Serial Input Bus
Window to Send TOH Bytes
D1, D2 and D3 for all 12 STS1's
on Serial Input Bus
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ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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