參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 55/105頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
53
Figure 29 shows the timing for sending data from the FPGA logic to the Core. In the input case, the constraints on
the data are specied in terms of setup and hold times on the data at the interface relative to the clock at the inter-
face. For correct operation these constraints must be met. In the case shown, launch and capture occur on the
same (rising) clock edge. Data is captured before the next data is launched, so there will be no hold margin prob-
lem. Launched data also has nearly a full clock period to become stable at the capture latch, so setup margin
should not be a problem.
Figure 29. Full Cycle, Align and Bypass Mode Input Conguration and Timing (-1 Speed Grade)
Q
+
D
+
Δ t
Embedded
Core
FPGA
Logic
3.0 ns
Primary Clock
1.4 ns
RETIME_CLK
a.) Configuration
a.) Timing (ns)
FPGA_CLK
FPGA_SYSCLK
2.4 ns
.
FPGA_SYSCLK
0.0
4.7
9.4
14.1
FPGA_CLK
3.0
7.7
12.4
17.1
Capture
- 1.7
1.0
5.7
10.4
15.1
setup time - 1.3
RETIME_CLK
Launch
Hold
Data Valid
DINxx[7:0]
hold time = 2.3
Requirements on
Δ t
Note: xx = [AA, AB, ..., BD]
DINxx[7:0]
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參數(shù)描述
ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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