參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 47/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
46
phases (i.e., received and system) are determined. This latch point is then stable unless the relative framing
changes and the received H byte times collide with the system F1 or E2 times, in which case the latch point would
be switched to the collision-free byte time.
There is no restriction on how many or how often increments and decrements are processed. Any received incre-
ment or decrement is immediately passed to the generator for implementation regardless of when the last pointer
adjustment was made. The responsibility for meeting the SONET criteria for maximum frequency of pointer adjust-
ments is left to an upstream pointer processor.
Receive Bypass Options
Not all of the blocks in the receive direction are required to be used. The following bypass options are valid in the
receive (backplane
→ FPGA) direction:
STM Pointer Mover bypass:
– In this mode, data from the alignment FIFOs is transferred to the FPGA logic. All channels are synchronous
to the FPGA_SYSCLK signals driven to the FPGA logic, as is also the case when the pointer mover is not
bypassed. During bypass SPE, C1J1, and data parity signals are not valid. When the pointer mover is
bypassed, eight frame pulses (DOUTxx_FP) from aligned channels are provided by the embedded core to
the FPGA.
– When the pointer mover is used, the FPGA logic provides the frame pulse on the LINE_FP (recall: there is
only one LINE_FP just like there is only one SYS_FP) signal essential for the Pointer Mover to move the
data. The FPGA gets eight channels of SONET data with the A1 byte position of each channel of the TOH
arbitrarily offset from the LINE_FP. The DOUTxx_FP signals are not valid when the pointer mover is used.
STM Pointer Mover and Alignment FIFO bypass:
– In this mode, data from the framer block is transferred to the FPGA logic. All channels supply data and frame
pulses synchronous with their individual recovered clock (CDR_CLK_xx) per channel. During bypass, SPE,
C1J1, and data parity signals are not valid. Additionally, no serial TOH_OUT_xx data and frame pulse sig-
nals will be available. The DOUTxx_FP signals are aligned with the A1 byte position of each channel, as
shown in Figure 26.
Figure 26. Pointer Mover and Alignment FIFO Bypass Timing
Table 14 shows the register settings to enable the bypass modes.
Table 14. Register Settings for Bypass Mode
Register Address
Value
Description
0x3000C
0x04
Turn off the SONET scrambler/descrambler
0x30020
0x07
Channel AA in functional mode
0x30038
0x07
Channel AB in functional mode
0x30050
0x07
Channel AC in functional mode
0x30068
0x07
Channel AD in functional mode
0x30080
0x07
Channel BA in functional mode
0x30098
0x07
Channel BB in functional mode
0x300B0
0x07
Channel BC in functional mode
0x300C8
0x07
Channel BD in functional mode
CDR_CLK_xx
DOUTxx
DOUTxx_FP
First A1 Byte
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