參數(shù)資料
型號： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 66/105頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
63
30019
[0:7]
-
Not Used
00
Channel Register Blocks
30020*
30038
30050
30068
30080
30098
300B0
300C8
[0]
R/W
AIS-L insert in
OOF
0
0 = When RX direction OOF occurs,
do not insert AIS-L.
1 = When RX direction OOF occurs, insert AIS-L.
[1]
R/W
AIS-L control
0
0 = Do not force AIS-L insert
1 = Always force AIS-L insert
[2]
R/W
TOH output par-
ity error insert
0
0 = Do not insert a parity error
1 = Insert parity error in parity bit of receive TOH serial out-
put for as long as this bit is set
[3]
R/W
RX K1/K2 source
select
0
0 = Set receive direction K1 K2 bytes to 0.
1 = Pass receive direction K1 K2 through pointer mover.
[4]
R/W
DOUTxx bus par-
ity error insert
0
0 = Do not insert parity error.
1 = Insert parity error in DOUTxx_PAR for as long as this
bit is set.
[5]
R/W
channel
enable/disable
control
0
0 = Power down CDR channels
1 = Functional mode.
[6]
R/W
DOUTxx_EN
0
DOUTxx_EN signal
[7]
R/W
TOH_EN
0
TOHxx_EN signal
30021*
30039
30051
30069
30081
30099
300B1
300C9
[0]
R/W
D9 source select
0
0 = Insert D9 from TOH_INxx
1 = Pass through D9 from DINxx
[1]
R/W
D10 source
select
0
0 = Insert D10 from TOH_INxx
1 = Pass through D10 from DINxx
[2]
R/W
D11 source
select
0
0 = Insert D11 from TOH_INxx
1 = Pass through D11 from DINxx
[3]
R/W
D12 source
select
0
0 = Insert D12 from TOH_INxx
1 = Pass through D12 from DINxx
[4]
R/W
K1 K2 source
select
0
0 = Insert K1, K2 from TOH_INxx
1 = Pass through K1, K2 from DINxx
[5]
R/W
S1 M0 source
select
0
0 = Insert S1, M0, from TOH_INxx
1 = Pass through S1 M0 of DINxx
[6]
R/W
E1 F1 E2 source
select
0 = Insert E1, F1, E2 from TOH_INxx on FPGA interface
1 = Pass through E1, F1, E2 TOH bytes of DINxx
[7]
R/W
TOH source
select
0
0 = Insert TOH from TOH_INxx on FPGA interface for
transmit
1 = Pass through all TOH DINxx for transmit
30022*
3003A
30052
3006A
30082
3009A
300B2
300CA
[0:7]
R/W
D1~D8 source
select
00
0 = Insert TOH for transmit from TOH_INxx from the FPGA
interface.
1 = Pass through D1~D8 TOH bytes from DINxx.
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description
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參數(shù)描述
ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT9303 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
ORT9303B 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
ORT9303BL 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
ORT9303G 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
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