參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 46/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
45
The pointer mover block can correctly process any length of concatenation of STS frames (multiple of three) as
long as it begins on an STS-3 boundary (i.e., STS-1 number one, four, seven, ten, etc.) and is contained within the
smaller of STS-3, 12, or 48. The pointer value can be adjusted to change the start of the SPE position and thereby
adjust for frequency changes. The variations in frequency are taken care of using justication.
When the incoming data rate exceeds the nominal rate, negative justication is used to compensate for the fre-
quency difference. Data are transmitted in the pointer action byte, H3, and thereby adjust for the additional incom-
ing data. The size of one SPE is still the same, but it is transmitted in less time than usual, and so a higher data rate
is achieved for some time. Negative justication causes the start of SPE to move left by one column or by decreas-
ing the pointer by one. The following frames contain the new pointer value.
Negative justication is indicated by inverting the D bits (bits 8, 10, 12, 14, 16) of the pointer word. The receiver
determines the occurrence of negative justication by examining these bits of the pointer word and applying a 5-bit
majority logic on them.
When the incoming data rate lags the nominal rate, positive justication is used to compensate for the frequency
difference. Data are not transmitted in the byte following the pointer action byte, H3, and thereby adjust for the lack
of incoming data. The size of one SPE is still the same, but it is transmitted in more time than usual, and hence a
slower data rate is achieved for some time. Positive justication causes the start of SPE to move right by one col-
umn or by increasing the pointer by one. The following frames contain the new pointer value.
Positive justication is indicated by inverting the I bits (bits 7, 9, 11, 13, 15) of the pointer word. The receiver deter-
mines the occurrence of positive justication by examining these bits of the pointer word and applying a 5-bit major-
ity logic on them.
The SPE signal to the FPGA logic must be high during negative stuff opportunity byte time slots (H3) for which valid
data is carried (negative stufng). SPE signal must be low during positive stuff opportunity byte time slots for which
there is no valid data (positive stufng). This behavior is shown in the following gure.
Figure 25. SPE Signal During Justication
In either justication, the pointer must remain unchanged for at least three consecutive frames before it can be jus-
tied again. The pointer can jump randomly to a new position at any point of time. This can happen in conditions
when the transmitting end has just recovered from an error condition. A sudden jump in the pointer value is indi-
cated through NDF, New Data Flag. This information is carried in the four MS bits of the pointer word. A 3-bit major-
ity logic is applied on the NDF bits to determine the status of the pointer jump.
Pointer Generator
The pointer generator maps the corresponding bytes into their appropriate location in the outgoing byte stream.
The generator also creates offset pointers based on the location of the J1 byte as indicated by the pointer inter-
preter. The generator will signal NDFs when the interpreter signals that it is coming out of AIS state. The pointer
generator resets the pointer value and generates NDF every time a byte marked J1 is read from the elastic store
that doesn't match the previous offset. Increment and decrement signals from the pointer interpreter are latched
once per frame on either the F1 or E2 byte times (depending on collisions); this ensures constant values during the
H1 through H3 times. The choice of which byte time to do the latching on is made once when the relative frame
STS-12
TOH ROW # 4
SPE ROW # 4
H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3
STS-12
SPE
POSITIVE STUFF
OPPORTUNITY BYTES
12
34
56 7
8 9 10 11 12
NEGATIVE STUFF
OPPORTUNITY BYTES
SPE SIGNAL SHOWS NEGATIVE STUFFING FOR 2ND STS-1,
AND POSITIVE STUFFING FOR 6TH STS-1
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ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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