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參數(shù)資料
| 型號： | MC68838FCC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 84/100頁 |
| 文件大?。?/td> | 465K |
| 代理商： | MC68838FCC |
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10-2
MC68838 USER’S MANUAL
MOTOROLA
Table 10-1. BIST Register Values
Register
Address
Test 1 Value
Test 2 Value
Test 3 Value
TX_Control
1
0200
82FF
13FF
My Short Address
10
7777
8888
137F
My Long Address A
11
AAAA
5555
37F1
My Long Address B
12
BBBB
4444
7F13
My Long Address C
13
CCCC
3333
F137
Target Request Time Register
14
FF00
00FF
FEC8
TVX, TRT Initial Timer Parameter Register
15
AACC
5533
F0FC
Interrupt Mask Register A
2
0000
Interrupt Mask Register B
3
0000
RC_Control (Run BIST)
0
88C4
F127
A414
Run BYTCLK until BIST_Done is indicated by
MACINT assertion
BIST Result Revision A MAC
2A
6148
0E9C
DED9
BIST Result Revision C MAC
2A
9FA2
7FB6
E93E
NOTE: All values are hexadecimal.
NOTE
BIST Test 3 is very sensitive to different implementations. If
your BIST signature for Test 3 differs from the one listed here,
please use that value if the chip is otherwise functional.
10.2 SCAN PATH OPERATION
Boundary scanning allows the user to shift an arbitrary bit pattern into the MAC to be used
for the corresponding input or output signal and to shift out the values of these signals
while holding the clock. The boundary scan chain includes every signal on the MAC
except
MATCH, the test signals, and the clocks.
Although boundary scanning complements BIST, which does not test these latches, the
main purpose of this test mode is for board testing. In this mode, the I/O latches of the
various chips on the board are linked into a large scan chain. By serially shifting data into
the scan chain (boundary scan serial test mode), then clocking the data in parallel (normal
or boundary scan parallel test mode), and finally serially shifting the data out, the I/O
latches and interconnections between the various chips can be tested on a PC board.
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