- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98011 > MC68838FCC (MOTOROLA INC) 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 PDF資料下載
參數(shù)資料
| 型號： | MC68838FCC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 55/100頁 |
| 文件大小： | 465K |
| 代理商： | MC68838FCC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
MOTOROLA
MC68838 USER’S MANUAL
4- 5
Transmit Parity (TPRITY)
This TTL-level input signal indicates the parity of the TPATHx bus; the TXCTLx lines are
not affected. The MAC expects either odd parity or no parity according to the
TX_PARITY_ON bit value in control register B. TPRITY is checked on every cycle,
including FILLER. This signal must be synchronous to BYTCLK.
Transmit Ready (TXRDY)
This output signal indicates to the FSI that the MAC is ready to accept additional
TXDATx transfers.
Abort Transmission (TABORT)
This output signal indicates to the FSI that it should abort this transmission. This signal
is asserted while the transmitter is turned off (i.e., MAC_ON = 0).
4.6 CAM INTERFACE
The CAM interface is a BYTCLK-synchronous interface used to connect the MAC to
external address or frame routing control recognition logic such as CAM chips, FSI internal
CAM, or source routing control logic.
Load Address/Transparent Bridge Forward (LDADDR/
TR_BR_FWD)
This bidirectional control signal is used for CAM interface. As a CMOS-level output,
LDADDR is pulsed high for one BYTCLK cycle just before the first byte of the DA or SA
field is presented on the RCDATx bus. As a TTL-level input,
TR_BR_FWD is used as a
match signal in the extended match timing mode as defined and controlled by the
EXT_DA_MATCH bit in control register B.
TR_BR_FWD is asserted low.
Address 16/Receive Abort 2 (
ADDR16/RABORT2)
This bidirectional control signal is used for CAM interface. As a CMOS-level output,
ADDR16 represents the last L-bit received. The L-bit is a bit in the FC field of all frames
and tokens. It is high when a frame with a 48-bit address field is received and low when
a frame with a 16-bit address field is received. It is high for restricted tokens and low for
unrestricted tokens. This line is synchronous with BYTCLK. As a TTL-level input,
RABORT2 provides a second abort signal to indicate that the MAC should abort the
incoming frame. The MAC will signal end of data to the FSI. The functionality of this
input is the same as the current RABORT input. This signal line is controlled by the
RABORT2 bit in control register B.
Destination Address (DA)
This CMOS-level output signal is used to indicate whether the address being presented
to the CAM is the DA or SA field of the received packet. This signal is low when the
MAC is receiving fields other than address fields.
ARCHIVE
INFORMA
TION
ARCHIVE
INFORMA
TION
相關PDF資料 |
PDF描述 |
|---|---|
| MC68EC020FG | 32-BIT, 25 MHz, MICROCONTROLLER, PQFP100 |
| MC68HC05CC1P | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC05CC2B | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PDIP42 |
| MC68HC05CT4FN | 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC05J1P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68840FE25B | 制造商:Motorola Inc 功能描述:68840FE25B |
| MC68840FE-25B | 制造商:Motorola Inc 功能描述:68840FE-25B |
| MC6885 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HEX THREE-STATE BUFFER/INVERTERS |
| MC68851 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Paged Memory Management Unit |
| MC6885L | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HEX THREE-STATE BUFFER/INVERTERS |
發(fā)布緊急采購，3分鐘左右您將得到回復。