參數(shù)資料
型號(hào)： MC68838FCC
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120
封裝： CERAMIC, QFP-120
文件頁(yè)數(shù)： 77/100頁(yè)
文件大?。?/td> 465K
代理商： MC68838FCC
9- 2
MC68838 USER’S MANUAL
MOTOROLA
negated by the MAC within one BYTCLK cycle after its assertion to enable the CAM
to properly load the address and perform the compare operation.
2. The first address byte of the SA or DA is valid on RCDATx during the BYTCLK cycle
following the assertion of LDADDR. This byte and the next five bytes of each
address are then consecutively loaded into the CAM. One BYTCLK cycle is then
allowed for the compare operation. The
MATCH signal must then be asserted to the
MAC on the eighth rising edge of BYTCLK after LDADDR has been negated to
indicate that the address is recognized and that the MAC should copy the frame. The
MATCH signal to the MAC is low if a match occurs.
3. DA is asserted with the frame's FC field, which means that DA has the same
functional timing as the LDADDR signal but remains asserted and valid up to the last
byte of the destination address. The
ADDR16 signal is asserted with the first byte of
the destination address.
BYTCLK
JK
FC
DA
1
DA
2
DA
3
DA
5
DA
4
DA
6
SA
1
SA
2
SA
3
SA
4
SA
5
SA
6
D1 D2
RCDAT
ADDR16
MATCH
DA
LDADDR
Figure 9-1. CAM Interface Signals (EXT_DA_MATCH = 0)
9.1.2 Extended Match Mode
When EXT_DA_MATCH = 1 in control register B, the user can respond to the MAC with a
MATCH through the second byte of the FCS (see Figure 9-2).
When the MAC is configured to accept later indications of a frame match by setting
EXT_DA_MATCH = 1, either the
MATCH or TR_BR_FWD signal can be activated during
any byte of the received frame from and including the second byte following the DA,
including the last byte of the FCS. This configuration means that the latest that either
signal may be asserted is a setup time before and a hold time after the next BYTCLK
cycle on which the last byte of the FCS appears on the RCDATx bus. Either RABORT or
ADDR16, configured as RABORT2, can be asserted at any time during frame reception to
cause the currently received frame to be flushed.
Figure 9-2 shows the sequence of events on the CAM interface when EXT_DA_MATCH is
programmed to one (for delayed address matching), which also causes the LDADDR
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