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參數(shù)資料
| 型號(hào)： | MC68838FCC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁(yè)數(shù)： | 78/100頁(yè) |
| 文件大?。?/td> | 465K |
| 代理商： | MC68838FCC |
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MOTOROLA
MC68838 USER’S MANUAL
9- 3
output signal to become
TR_BR_FWD, an additional input signal for bridge address
matching logic. The
TR_BR_FWD signal has the same timing as the MATCH signal and is
used to specifically indicate an address match with the effect on the A and C frame status
indicators as shown in Figure 9-2. Both the
TR_BR_FWD and MATCH signal can be used
on the same implementation. Either input can be asserted any time from the second byte
of the SA up to and including the fourth byte of the FCS. The
MATCH signal has the effect
of setting the A bit and overrides the
TR_BR_FWD input.
BYTCLK
JK FC
DA
1
DA
2
DA
3
DA
5
DA
4
DA
6
Dn
RCDAT
ADDR16
DA
FCS
1
FCS
2
FCS
3
MATCH
or TR_BR_FWD
SA
1
SA
2
FCS
4
RABORT OR
RABORT2
VALID ASSERTION RANGE
Figure 9-2. CAM Interface Signals (EXT_DA_MATCH = 1)
Figure 9-3 shows the sequence of events on the CAM interface when receiving a token
frame for both normal and extended match mode. DA is asserted for one or two BYTCLKs
when a token is received. A two BYTCLK assertion is shown.
BYTCLK
FC
TT
II
RCDAT
ADDR16
DA
II
JK
FC
TT
II
LDADDR
UNRESTRICTED TOKEN
RESTRICTED TOKEN
JK
Figure 9-3. CAM Interface Timing (Receiving Token
Frame for Normal and Extended Match Mode)
ARCHIVE
INFORMA
TION
ARCHIVE
INFORMA
TION
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