參數(shù)資料
型號: MC68838FCC
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120
封裝: CERAMIC, QFP-120
文件頁數(shù): 51/100頁
文件大?。?/td> 465K
代理商: MC68838FCC
MOTOROLA
MC68838 USER’S MANUAL
4- 1
SECTION 4
SIGNAL DESCRIPTION
This section describes the MAC signals. The MAC is intended to interface with the FSI
device and the ELM device as a physical media interface. Figure 4-1 illustrates the
functional group pinout of the MAC
CLOCKS AND
CONTROL
NODE PROCESSOR
INTERFACE
TEST INTERFACE
ELM INTERFACE
CAM
INTERFACE
TABORT
TXRDY
RCCTL4–RCCTL0
RPRITY
RPATH7–RPATH0
ADDR16/RABORT2
LDADDR/TR_BR_FWD
TXDAT9–TXDAT0
MSCANO
MPTSTO
MACINT
NPD15–NPD0
PWRUP
NPCLK
RECEIVE DATA
SYSTEM INTERFACE
TRANSMIT DATA
SYSTEM INTERFACE
TPATH7–TPATH0
TPRITY
TXCTL1–TXCTL0
RABORT
MATCH
RCDAT9–RCDAT0
MSCANI
MTEST1–MTEST0
NPRW
NPA5–NPA0
MACSEL
BYTCLK
SYMCLK
DA
Figure 4-1. MAC Functional Pinout
4.1 CLOCK SIGNALS
These signals are used to clock and power up the chip.
Byte Clock (BYTCLK)
This TTL-level-compatible input signal has a cycle time of 12.5 MHz during normal
operation. The rising edge, 0 to 5 V, of BYTCLK defines the beginning of a new cycle
and is used to sample some input lines and to allow the chip to start presenting new
values on all output lines.
ARCHIVE
INFORMA
TION
ARCHIVE
INFORMA
TION
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