參數(shù)資料
型號(hào)： MC68838FCC
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120
封裝： CERAMIC, QFP-120
文件頁數(shù)： 62/100頁
文件大?。?/td> 465K
代理商： MC68838FCC
MOTOROLA
MC68838 USER’S MANUAL
6-1
SECTION 6
MAC-PHY INTERFACE OPERATION
The MAC-PHY interface links the MAC chip to the ELM. These buses are synchronous
with BYTCLK. There is no parity on the MAC-PHY interface since the data is protected by
the packet's FCS field (a 32-bit CRC).
The MAC will never generate a halt (H), quiet (Q), or violation (V) symbol nor signal a
PHY_INVALID to the PHY layer (ELM). The response of the MAC is undefined when it is
passed a code that is not listed in the data link code column of Table 6-1. The highest
order bit (bit 9) is the first bit of the symbol pair sent out on the PHY media on TXDATx
and the first bit received from the PHY media on RCDATx. The data symbol pair on
RCDATx and TXDATx is encoded in data link form as shown in Table 6-1
Table 6-1. RCDATx/TXDATx Encoding
Symbol
Data Link
Code
Symbol
Data Link
Code
0
00000
H
10100
1
00001
H
10100
2
00010
H
10100
3
00011
H
10100
4
00100
H
10100
5
00101
I
10111
6
00110
J
11100
7
00111
K
10011
8
01000
Q
10000
9
01001
R
10001
A
01010
S
11001
B
01011
T
11101
C
01100
V
11000
D
01101
V
11000
E
01110
V
11000
F
01111
V
11000
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